tsunami-simple-atomic.py revision 6122:9af6fb59752f
19380SAndreas.Sandberg@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 29380SAndreas.Sandberg@ARM.com# All rights reserved. 39380SAndreas.Sandberg@ARM.com# 49380SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 59380SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 69380SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 79380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 89380SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 99380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 109380SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 119380SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 129380SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 139380SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 149380SAndreas.Sandberg@ARM.com# 159380SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169380SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179380SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189380SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199380SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209380SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219380SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229380SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239380SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249380SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259380SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269380SAndreas.Sandberg@ARM.com# 279380SAndreas.Sandberg@ARM.com# Authors: Steve Reinhardt 289380SAndreas.Sandberg@ARM.com 299380SAndreas.Sandberg@ARM.comimport m5 309380SAndreas.Sandberg@ARM.comfrom m5.objects import * 319380SAndreas.Sandberg@ARM.comm5.AddToPath('../configs/common') 329380SAndreas.Sandberg@ARM.comimport FSConfig 339380SAndreas.Sandberg@ARM.com 349380SAndreas.Sandberg@ARM.com# -------------------- 359380SAndreas.Sandberg@ARM.com# Base L1 Cache 369380SAndreas.Sandberg@ARM.com# ==================== 379380SAndreas.Sandberg@ARM.com 389380SAndreas.Sandberg@ARM.comclass L1(BaseCache): 399380SAndreas.Sandberg@ARM.com latency = '1ns' 409380SAndreas.Sandberg@ARM.com block_size = 64 419380SAndreas.Sandberg@ARM.com mshrs = 4 429380SAndreas.Sandberg@ARM.com tgts_per_mshr = 8 439380SAndreas.Sandberg@ARM.com 449380SAndreas.Sandberg@ARM.com# ---------------------- 459380SAndreas.Sandberg@ARM.com# Base L2 Cache 469380SAndreas.Sandberg@ARM.com# ---------------------- 479380SAndreas.Sandberg@ARM.com 489380SAndreas.Sandberg@ARM.comclass L2(BaseCache): 499380SAndreas.Sandberg@ARM.com block_size = 64 509380SAndreas.Sandberg@ARM.com latency = '10ns' 519380SAndreas.Sandberg@ARM.com mshrs = 92 529380SAndreas.Sandberg@ARM.com tgts_per_mshr = 16 539380SAndreas.Sandberg@ARM.com write_buffers = 8 549380SAndreas.Sandberg@ARM.com 559380SAndreas.Sandberg@ARM.com# --------------------- 569380SAndreas.Sandberg@ARM.com# I/O Cache 579380SAndreas.Sandberg@ARM.com# --------------------- 589380SAndreas.Sandberg@ARM.comclass IOCache(BaseCache): 599380SAndreas.Sandberg@ARM.com assoc = 8 609380SAndreas.Sandberg@ARM.com block_size = 64 619380SAndreas.Sandberg@ARM.com latency = '50ns' 629380SAndreas.Sandberg@ARM.com mshrs = 20 639380SAndreas.Sandberg@ARM.com size = '1kB' 649380SAndreas.Sandberg@ARM.com tgts_per_mshr = 12 659380SAndreas.Sandberg@ARM.com addr_range=AddrRange(0, size='8GB') 669380SAndreas.Sandberg@ARM.com forward_snoops = False 679380SAndreas.Sandberg@ARM.com 689380SAndreas.Sandberg@ARM.com#cpu 699380SAndreas.Sandberg@ARM.comcpu = AtomicSimpleCPU(cpu_id=0) 709380SAndreas.Sandberg@ARM.com#the system 719380SAndreas.Sandberg@ARM.comsystem = FSConfig.makeLinuxAlphaSystem('atomic') 729380SAndreas.Sandberg@ARM.comsystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 739380SAndreas.Sandberg@ARM.comsystem.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] 749380SAndreas.Sandberg@ARM.comsystem.iocache = IOCache() 759380SAndreas.Sandberg@ARM.comsystem.iocache.cpu_side = system.iobus.port 769380SAndreas.Sandberg@ARM.comsystem.iocache.mem_side = system.membus.port 779380SAndreas.Sandberg@ARM.com 789380SAndreas.Sandberg@ARM.comsystem.cpu = cpu 799380SAndreas.Sandberg@ARM.com#create the l1/l2 bus 809380SAndreas.Sandberg@ARM.comsystem.toL2Bus = Bus() 819380SAndreas.Sandberg@ARM.com 829380SAndreas.Sandberg@ARM.com#connect up the l2 cache 839380SAndreas.Sandberg@ARM.comsystem.l2c = L2(size='4MB', assoc=8) 849380SAndreas.Sandberg@ARM.comsystem.l2c.cpu_side = system.toL2Bus.port 859380SAndreas.Sandberg@ARM.comsystem.l2c.mem_side = system.membus.port 869380SAndreas.Sandberg@ARM.com 879380SAndreas.Sandberg@ARM.com#connect up the cpu and l1s 889380SAndreas.Sandberg@ARM.comcpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 899380SAndreas.Sandberg@ARM.com L1(size = '32kB', assoc = 4)) 909380SAndreas.Sandberg@ARM.com# connect cpu level-1 caches to shared level-2 cache 919380SAndreas.Sandberg@ARM.comcpu.connectMemPorts(system.toL2Bus) 929380SAndreas.Sandberg@ARM.comcpu.clock = '2GHz' 939380SAndreas.Sandberg@ARM.com 949380SAndreas.Sandberg@ARM.comroot = Root(system=system) 959380SAndreas.Sandberg@ARM.comm5.ticks.setGlobalFrequency('1THz') 969447SAndreas.Sandberg@ARM.com 979447SAndreas.Sandberg@ARM.com