tsunami-simple-atomic-dual.py revision 9310:aa7bf10e822a 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Caches import *
34
35#cpu
36cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
37#the system
38system = FSConfig.makeLinuxAlphaSystem('atomic')
39system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
40system.iocache.cpu_side = system.iobus.master
41system.iocache.mem_side = system.membus.slave
42
43system.cpu = cpus
44#create the l1/l2 bus
45system.toL2Bus = CoherentBus(clock = '2GHz')
46
47#connect up the l2 cache
48system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
49system.l2c.cpu_side = system.toL2Bus.master
50system.l2c.mem_side = system.membus.slave
51
52#connect up the cpu and l1s
53for c in cpus:
54    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
55                                L1(size = '32kB', assoc = 4))
56    # create the interrupt controller
57    c.createInterruptController()
58    # connect cpu level-1 caches to shared level-2 cache
59    c.connectAllPorts(system.toL2Bus, system.membus)
60    c.clock = '2GHz'
61
62root = Root(full_system=True, system=system)
63m5.ticks.setGlobalFrequency('1THz')
64