tsunami-simple-atomic-dual.py revision 6122:9af6fb59752f
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39    latency = '1ns'
40    block_size = 64
41    mshrs = 4
42    tgts_per_mshr = 8
43
44# ----------------------
45# Base L2 Cache
46# ----------------------
47
48class L2(BaseCache):
49    block_size = 64
50    latency = '10ns'
51    mshrs = 92
52    tgts_per_mshr = 16
53    write_buffers = 8
54
55# ---------------------
56# I/O Cache
57# ---------------------
58class IOCache(BaseCache):
59    assoc = 8
60    block_size = 64
61    latency = '50ns'
62    mshrs = 20
63    size = '1kB'
64    tgts_per_mshr = 12
65    addr_range=AddrRange(0, size='8GB')
66    forward_snoops = False
67
68#cpu
69cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
70#the system
71system = FSConfig.makeLinuxAlphaSystem('atomic')
72system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
73system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
74system.iocache = IOCache()
75system.iocache.cpu_side = system.iobus.port
76system.iocache.mem_side = system.membus.port
77
78system.cpu = cpus
79#create the l1/l2 bus
80system.toL2Bus = Bus()
81
82#connect up the l2 cache
83system.l2c = L2(size='4MB', assoc=8)
84system.l2c.cpu_side = system.toL2Bus.port
85system.l2c.mem_side = system.membus.port
86
87#connect up the cpu and l1s
88for c in cpus:
89    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
90                                L1(size = '32kB', assoc = 4))
91    # connect cpu level-1 caches to shared level-2 cache
92    c.connectMemPorts(system.toL2Bus)
93    c.clock = '2GHz'
94
95root = Root(system=system)
96m5.ticks.setGlobalFrequency('1THz')
97