tsunami-o3.py revision 8631:8c038d4cd210
17404SAli.Saidi@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27404SAli.Saidi@ARM.com# All rights reserved. 37404SAli.Saidi@ARM.com# 47404SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 57404SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 67404SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 77404SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 87404SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 97404SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 107404SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 117404SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 127404SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 137404SAli.Saidi@ARM.com# this software without specific prior written permission. 147404SAli.Saidi@ARM.com# 157404SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167404SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177404SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187404SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197404SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207404SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217404SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227404SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237404SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247404SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257404SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267404SAli.Saidi@ARM.com# 277404SAli.Saidi@ARM.com# Authors: Steve Reinhardt 287404SAli.Saidi@ARM.com 297404SAli.Saidi@ARM.comimport m5 307404SAli.Saidi@ARM.comfrom m5.objects import * 317404SAli.Saidi@ARM.comm5.util.addToPath('../configs/common') 327404SAli.Saidi@ARM.comimport FSConfig 337404SAli.Saidi@ARM.com 347404SAli.Saidi@ARM.com 357404SAli.Saidi@ARM.com# -------------------- 367404SAli.Saidi@ARM.com# Base L1 Cache 377404SAli.Saidi@ARM.com# ==================== 387404SAli.Saidi@ARM.com 397404SAli.Saidi@ARM.comclass L1(BaseCache): 407404SAli.Saidi@ARM.com latency = '1ns' 417404SAli.Saidi@ARM.com block_size = 64 427404SAli.Saidi@ARM.com mshrs = 4 437578Sdam.sunwoo@arm.com tgts_per_mshr = 20 447578Sdam.sunwoo@arm.com is_top_level = True 457404SAli.Saidi@ARM.com 467404SAli.Saidi@ARM.com# ---------------------- 477404SAli.Saidi@ARM.com# Base L2 Cache 487404SAli.Saidi@ARM.com# ---------------------- 497404SAli.Saidi@ARM.com 507404SAli.Saidi@ARM.comclass L2(BaseCache): 517404SAli.Saidi@ARM.com block_size = 64 527404SAli.Saidi@ARM.com latency = '10ns' 537404SAli.Saidi@ARM.com mshrs = 92 547404SAli.Saidi@ARM.com tgts_per_mshr = 16 557404SAli.Saidi@ARM.com write_buffers = 8 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.com# --------------------- 587404SAli.Saidi@ARM.com# I/O Cache 597404SAli.Saidi@ARM.com# --------------------- 607404SAli.Saidi@ARM.comclass IOCache(BaseCache): 617404SAli.Saidi@ARM.com assoc = 8 627404SAli.Saidi@ARM.com block_size = 64 637404SAli.Saidi@ARM.com latency = '50ns' 647404SAli.Saidi@ARM.com mshrs = 20 657404SAli.Saidi@ARM.com size = '1kB' 667404SAli.Saidi@ARM.com tgts_per_mshr = 12 677404SAli.Saidi@ARM.com addr_range=AddrRange(0, size='8GB') 687404SAli.Saidi@ARM.com forward_snoops = False 697404SAli.Saidi@ARM.com is_top_level = True 707404SAli.Saidi@ARM.com 717404SAli.Saidi@ARM.com#cpu 727404SAli.Saidi@ARM.comcpu = DerivO3CPU(cpu_id=0) 737436Sdam.sunwoo@arm.com#the system 747404SAli.Saidi@ARM.comsystem = FSConfig.makeLinuxAlphaSystem('timing') 757404SAli.Saidi@ARM.com 767436Sdam.sunwoo@arm.comsystem.cpu = cpu 777436Sdam.sunwoo@arm.com#create the l1/l2 bus 787436Sdam.sunwoo@arm.comsystem.toL2Bus = Bus() 797436Sdam.sunwoo@arm.comsystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 807404SAli.Saidi@ARM.comsystem.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] 817404SAli.Saidi@ARM.comsystem.iocache = IOCache() 827404SAli.Saidi@ARM.comsystem.iocache.cpu_side = system.iobus.port 837404SAli.Saidi@ARM.comsystem.iocache.mem_side = system.membus.port 847404SAli.Saidi@ARM.com 857404SAli.Saidi@ARM.com 867404SAli.Saidi@ARM.com#connect up the l2 cache 877404SAli.Saidi@ARM.comsystem.l2c = L2(size='4MB', assoc=8) 887404SAli.Saidi@ARM.comsystem.l2c.cpu_side = system.toL2Bus.port 897404SAli.Saidi@ARM.comsystem.l2c.mem_side = system.membus.port 907404SAli.Saidi@ARM.com 917404SAli.Saidi@ARM.com#connect up the cpu and l1s 927404SAli.Saidi@ARM.comcpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 937404SAli.Saidi@ARM.com L1(size = '32kB', assoc = 4)) 947404SAli.Saidi@ARM.com# connect cpu level-1 caches to shared level-2 cache 957404SAli.Saidi@ARM.comcpu.connectAllPorts(system.toL2Bus, system.membus) 967404SAli.Saidi@ARM.comcpu.clock = '2GHz' 977404SAli.Saidi@ARM.com 987404SAli.Saidi@ARM.comroot = Root(system=system) 997404SAli.Saidi@ARM.comm5.ticks.setGlobalFrequency('1THz') 1007404SAli.Saidi@ARM.com 1017404SAli.Saidi@ARM.com