tsunami-o3-dual.py revision 9263:066099902102
112808Srobert.scheffel1@tu-dresden.de# Copyright (c) 2006-2007 The Regents of The University of Michigan 212808Srobert.scheffel1@tu-dresden.de# All rights reserved. 312808Srobert.scheffel1@tu-dresden.de# 412808Srobert.scheffel1@tu-dresden.de# Redistribution and use in source and binary forms, with or without 512808Srobert.scheffel1@tu-dresden.de# modification, are permitted provided that the following conditions are 612808Srobert.scheffel1@tu-dresden.de# met: redistributions of source code must retain the above copyright 712808Srobert.scheffel1@tu-dresden.de# notice, this list of conditions and the following disclaimer; 812808Srobert.scheffel1@tu-dresden.de# redistributions in binary form must reproduce the above copyright 912808Srobert.scheffel1@tu-dresden.de# notice, this list of conditions and the following disclaimer in the 1012808Srobert.scheffel1@tu-dresden.de# documentation and/or other materials provided with the distribution; 1112808Srobert.scheffel1@tu-dresden.de# neither the name of the copyright holders nor the names of its 1212808Srobert.scheffel1@tu-dresden.de# contributors may be used to endorse or promote products derived from 1312808Srobert.scheffel1@tu-dresden.de# this software without specific prior written permission. 1412808Srobert.scheffel1@tu-dresden.de# 1512808Srobert.scheffel1@tu-dresden.de# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1612808Srobert.scheffel1@tu-dresden.de# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1712808Srobert.scheffel1@tu-dresden.de# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1812808Srobert.scheffel1@tu-dresden.de# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1912808Srobert.scheffel1@tu-dresden.de# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2012808Srobert.scheffel1@tu-dresden.de# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2112808Srobert.scheffel1@tu-dresden.de# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2212808Srobert.scheffel1@tu-dresden.de# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2312808Srobert.scheffel1@tu-dresden.de# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2412808Srobert.scheffel1@tu-dresden.de# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2512808Srobert.scheffel1@tu-dresden.de# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2612808Srobert.scheffel1@tu-dresden.de# 2712808Srobert.scheffel1@tu-dresden.de# Authors: Steve Reinhardt 2812808Srobert.scheffel1@tu-dresden.de 2912808Srobert.scheffel1@tu-dresden.deimport m5 3012808Srobert.scheffel1@tu-dresden.defrom m5.objects import * 3112808Srobert.scheffel1@tu-dresden.dem5.util.addToPath('../configs/common') 3212808Srobert.scheffel1@tu-dresden.deimport FSConfig 3312808Srobert.scheffel1@tu-dresden.de 3412808Srobert.scheffel1@tu-dresden.de 3512808Srobert.scheffel1@tu-dresden.de# -------------------- 3612808Srobert.scheffel1@tu-dresden.de# Base L1 Cache 3712808Srobert.scheffel1@tu-dresden.de# ==================== 3812808Srobert.scheffel1@tu-dresden.de 3912808Srobert.scheffel1@tu-dresden.declass L1(BaseCache): 4012808Srobert.scheffel1@tu-dresden.de hit_latency = '1ns' 4112808Srobert.scheffel1@tu-dresden.de response_latency = '1ns' 4212808Srobert.scheffel1@tu-dresden.de block_size = 64 4312808Srobert.scheffel1@tu-dresden.de mshrs = 4 4412808Srobert.scheffel1@tu-dresden.de tgts_per_mshr = 20 4512808Srobert.scheffel1@tu-dresden.de is_top_level = True 4612808Srobert.scheffel1@tu-dresden.de 4712808Srobert.scheffel1@tu-dresden.de# ---------------------- 4812808Srobert.scheffel1@tu-dresden.de# Base L2 Cache 4912808Srobert.scheffel1@tu-dresden.de# ---------------------- 5012808Srobert.scheffel1@tu-dresden.de 5112808Srobert.scheffel1@tu-dresden.declass L2(BaseCache): 5212808Srobert.scheffel1@tu-dresden.de block_size = 64 53 hit_latency = '10ns' 54 response_latency = '10ns' 55 mshrs = 92 56 tgts_per_mshr = 16 57 write_buffers = 8 58 59# --------------------- 60# I/O Cache 61# --------------------- 62class IOCache(BaseCache): 63 assoc = 8 64 block_size = 64 65 hit_latency = '50ns' 66 response_latency = '50ns' 67 mshrs = 20 68 size = '1kB' 69 tgts_per_mshr = 12 70 addr_ranges = [AddrRange(0, size='8GB')] 71 forward_snoops = False 72 is_top_level = True 73 74#cpu 75cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] 76#the system 77system = FSConfig.makeLinuxAlphaSystem('timing') 78 79system.cpu = cpus 80#create the l1/l2 bus 81system.toL2Bus = CoherentBus() 82system.iocache = IOCache() 83system.iocache.cpu_side = system.iobus.master 84system.iocache.mem_side = system.membus.slave 85 86 87#connect up the l2 cache 88system.l2c = L2(size='4MB', assoc=8) 89system.l2c.cpu_side = system.toL2Bus.master 90system.l2c.mem_side = system.membus.slave 91 92#connect up the cpu and l1s 93for c in cpus: 94 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 95 L1(size = '32kB', assoc = 4)) 96 # create the interrupt controller 97 c.createInterruptController() 98 # connect cpu level-1 caches to shared level-2 cache 99 c.connectAllPorts(system.toL2Bus, system.membus) 100 c.clock = '2GHz' 101 102root = Root(full_system=True, system=system) 103m5.ticks.setGlobalFrequency('1THz') 104 105