tsunami-o3-dual.py revision 8801:1a84c6a81299 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33
34
35# --------------------
36# Base L1 Cache
37# ====================
38
39class L1(BaseCache):
40    latency = '1ns'
41    block_size = 64
42    mshrs = 4
43    tgts_per_mshr = 20
44    is_top_level = True
45
46# ----------------------
47# Base L2 Cache
48# ----------------------
49
50class L2(BaseCache):
51    block_size = 64
52    latency = '10ns'
53    mshrs = 92
54    tgts_per_mshr = 16
55    write_buffers = 8
56
57# ---------------------
58# I/O Cache
59# ---------------------
60class IOCache(BaseCache):
61    assoc = 8
62    block_size = 64
63    latency = '50ns'
64    mshrs = 20
65    size = '1kB'
66    tgts_per_mshr = 12
67    addr_range=AddrRange(0, size='8GB')
68    forward_snoops = False
69    is_top_level = True
70
71#cpu
72cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
73#the system
74system = FSConfig.makeLinuxAlphaSystem('timing')
75
76system.cpu = cpus
77#create the l1/l2 bus
78system.toL2Bus = Bus()
79system.iocache = IOCache()
80system.iocache.cpu_side = system.iobus.port
81system.iocache.mem_side = system.membus.port
82
83
84#connect up the l2 cache
85system.l2c = L2(size='4MB', assoc=8)
86system.l2c.cpu_side = system.toL2Bus.port
87system.l2c.mem_side = system.membus.port
88system.l2c.num_cpus = 2
89
90#connect up the cpu and l1s
91for c in cpus:
92    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
93                                L1(size = '32kB', assoc = 4))
94    # connect cpu level-1 caches to shared level-2 cache
95    c.connectAllPorts(system.toL2Bus, system.membus)
96    c.clock = '2GHz'
97
98root = Root(full_system=True, system=system)
99m5.ticks.setGlobalFrequency('1THz')
100
101