tsunami-o3-dual.py revision 5703
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 21762SN/A# All rights reserved. 32SN/A# 42SN/A# Redistribution and use in source and binary forms, with or without 52SN/A# modification, are permitted provided that the following conditions are 62SN/A# met: redistributions of source code must retain the above copyright 72SN/A# notice, this list of conditions and the following disclaimer; 82SN/A# redistributions in binary form must reproduce the above copyright 92SN/A# notice, this list of conditions and the following disclaimer in the 102SN/A# documentation and/or other materials provided with the distribution; 112SN/A# neither the name of the copyright holders nor the names of its 122SN/A# contributors may be used to endorse or promote products derived from 132SN/A# this software without specific prior written permission. 142SN/A# 152SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 282665Ssaidi@eecs.umich.edu 292SN/Aimport m5 302SN/Afrom m5.objects import * 312SN/Am5.AddToPath('../configs/common') 322SN/Aimport FSConfig 33601SN/A 34601SN/A 35601SN/A# -------------------- 3685SN/A# Base L1 Cache 3756SN/A# ==================== 3856SN/A 391127SN/Aclass L1(BaseCache): 40695SN/A latency = '1ns' 412SN/A block_size = 64 422SN/A mshrs = 4 432SN/A tgts_per_mshr = 8 442SN/A 452SN/A# ---------------------- 462SN/A# Base L2 Cache 472SN/A# ---------------------- 482SN/A 492SN/Aclass L2(BaseCache): 502SN/A block_size = 64 512SN/A latency = '10ns' 522SN/A mshrs = 92 532SN/A tgts_per_mshr = 16 542SN/A write_buffers = 8 552SN/A 562SN/A# --------------------- 572SN/A# I/O Cache 582SN/A# --------------------- 592SN/Aclass IOCache(BaseCache): 602SN/A assoc = 8 612SN/A block_size = 64 622SN/A latency = '50ns' 632SN/A mshrs = 20 642SN/A size = '1kB' 652SN/A tgts_per_mshr = 12 662SN/A mem_side_filter_ranges=[AddrRange(0, Addr.max)] 672SN/A cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] 682SN/A 692SN/A#cpu 702SN/Acpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] 712SN/A#the system 722SN/Asystem = FSConfig.makeLinuxAlphaSystem('timing') 732SN/A 742SN/Asystem.cpu = cpus 75396SN/A#create the l1/l2 bus 762SN/Asystem.toL2Bus = Bus() 772SN/Asystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 782SN/Asystem.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] 792SN/Asystem.iocache = IOCache() 802SN/Asystem.iocache.cpu_side = system.iobus.port 812SN/Asystem.iocache.mem_side = system.membus.port 82396SN/A 832SN/A 842SN/A#connect up the l2 cache 852SN/Asystem.l2c = L2(size='4MB', assoc=8) 862SN/Asystem.l2c.cpu_side = system.toL2Bus.port 872SN/Asystem.l2c.mem_side = system.membus.port 882SN/A 892SN/A#connect up the cpu and l1s 902SN/Afor c in cpus: 912SN/A c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 922SN/A L1(size = '32kB', assoc = 4)) 93392SN/A # connect cpu level-1 caches to shared level-2 cache 942SN/A c.connectMemPorts(system.toL2Bus) 952SN/A c.clock = '2GHz' 962SN/A 972SN/Aroot = Root(system=system) 982SN/Am5.ticks.setGlobalFrequency('1THz') 992SN/A 1002SN/A