tgen-simple-mem.py revision 9793
19242Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited
29242Sandreas.hansson@arm.com# All rights reserved.
39242Sandreas.hansson@arm.com#
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229242Sandreas.hansson@arm.com# this software without specific prior written permission.
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259242Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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359242Sandreas.hansson@arm.com#
369242Sandreas.hansson@arm.com# Authors: Andreas Hansson
379242Sandreas.hansson@arm.com
389242Sandreas.hansson@arm.comimport m5
399242Sandreas.hansson@arm.comfrom m5.objects import *
409242Sandreas.hansson@arm.com
419402Sandreas.hansson@arm.com# both traffic generator and communication monitor are only available
429402Sandreas.hansson@arm.com# if we have protobuf support, so potentially skip this test
439402Sandreas.hansson@arm.comrequire_sim_object("TrafficGen")
449402Sandreas.hansson@arm.comrequire_sim_object("CommMonitor")
459402Sandreas.hansson@arm.com
469242Sandreas.hansson@arm.com# even if this is only a traffic generator, call it cpu to make sure
479242Sandreas.hansson@arm.com# the scripts are happy
489242Sandreas.hansson@arm.comcpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
499242Sandreas.hansson@arm.com
509242Sandreas.hansson@arm.com# system simulated
519242Sandreas.hansson@arm.comsystem = System(cpu = cpu, physmem = SimpleMemory(),
529793Sakash.bagdia@arm.com                membus = NoncoherentBus(width = 16),
539793Sakash.bagdia@arm.com                clk_domain = SrcClockDomain(clock = '1GHz'))
549242Sandreas.hansson@arm.com
559398Sandreas.hansson@arm.com# add a communication monitor, and also trace all the packets
569398Sandreas.hansson@arm.comsystem.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
579242Sandreas.hansson@arm.com
589242Sandreas.hansson@arm.com# connect the traffic generator to the bus via a communication monitor
599242Sandreas.hansson@arm.comsystem.cpu.port = system.monitor.slave
609242Sandreas.hansson@arm.comsystem.monitor.master = system.membus.slave
619242Sandreas.hansson@arm.com
629242Sandreas.hansson@arm.com# connect the system port even if it is not used in this example
639242Sandreas.hansson@arm.comsystem.system_port = system.membus.slave
649242Sandreas.hansson@arm.com
659242Sandreas.hansson@arm.com# connect memory to the membus
669242Sandreas.hansson@arm.comsystem.physmem.port = system.membus.master
679242Sandreas.hansson@arm.com
689242Sandreas.hansson@arm.com# -----------------------
699242Sandreas.hansson@arm.com# run simulation
709242Sandreas.hansson@arm.com# -----------------------
719242Sandreas.hansson@arm.com
729242Sandreas.hansson@arm.comroot = Root(full_system = False, system = system)
739242Sandreas.hansson@arm.comroot.system.mem_mode = 'timing'
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