tgen-simple-mem.py revision 9242
12553SN/A# Copyright (c) 2012 ARM Limited 22553SN/A# All rights reserved. 32553SN/A# 42553SN/A# The license below extends only to copyright in the software and shall 52553SN/A# not be construed as granting a license to any other intellectual 62553SN/A# property including but not limited to intellectual property relating 72553SN/A# to a hardware implementation of the functionality of the software 82553SN/A# licensed hereunder. You may use the software subject to the license 92553SN/A# terms below provided that you ensure that this notice is replicated 102553SN/A# unmodified and in its entirety in all distributions of the software, 112553SN/A# modified or unmodified, in source code or in binary form. 122553SN/A# 132553SN/A# Redistribution and use in source and binary forms, with or without 142553SN/A# modification, are permitted provided that the following conditions are 152553SN/A# met: redistributions of source code must retain the above copyright 162553SN/A# notice, this list of conditions and the following disclaimer; 172553SN/A# redistributions in binary form must reproduce the above copyright 182553SN/A# notice, this list of conditions and the following disclaimer in the 192553SN/A# documentation and/or other materials provided with the distribution; 202553SN/A# neither the name of the copyright holders nor the names of its 212553SN/A# contributors may be used to endorse or promote products derived from 222553SN/A# this software without specific prior written permission. 232553SN/A# 242553SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252553SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262553SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272665Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282665Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292553SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302553SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 315569Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 325569Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332553SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3413536Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352553SN/A# 362553SN/A# Authors: Andreas Hansson 372553SN/A 382553SN/Aimport m5 392553SN/Afrom m5.objects import * 402553SN/A 412553SN/A# even if this is only a traffic generator, call it cpu to make sure 422553SN/A# the scripts are happy 432553SN/Acpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") 442553SN/A 4511382Sbrandon.potter@amd.com# system simulated 4611382Sbrandon.potter@amd.comsystem = System(cpu = cpu, physmem = SimpleMemory(), 4711382Sbrandon.potter@amd.com membus = NoncoherentBus(clock="1GHz", width = 16)) 4811382Sbrandon.potter@amd.com 4911382Sbrandon.potter@amd.com# add a communication monitor 5011382Sbrandon.potter@amd.comsystem.monitor = CommMonitor() 5111382Sbrandon.potter@amd.com 5211382Sbrandon.potter@amd.com# connect the traffic generator to the bus via a communication monitor 5311382Sbrandon.potter@amd.comsystem.cpu.port = system.monitor.slave 5411382Sbrandon.potter@amd.comsystem.monitor.master = system.membus.slave 5511382Sbrandon.potter@amd.com 5611382Sbrandon.potter@amd.com# connect the system port even if it is not used in this example 5711382Sbrandon.potter@amd.comsystem.system_port = system.membus.slave 5811382Sbrandon.potter@amd.com 5911382Sbrandon.potter@amd.com# connect memory to the membus 6011382Sbrandon.potter@amd.comsystem.physmem.port = system.membus.master 6111382Sbrandon.potter@amd.com 6211382Sbrandon.potter@amd.com# ----------------------- 6311382Sbrandon.potter@amd.com# run simulation 6411382Sbrandon.potter@amd.com# ----------------------- 6511382Sbrandon.potter@amd.com 6611382Sbrandon.potter@amd.comroot = Root(full_system = False, system = system) 6711382Sbrandon.potter@amd.comroot.system.mem_mode = 'timing' 6811382Sbrandon.potter@amd.com