simple-timing-ruby.py revision 7570:417ef5d444bd
19243SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 211675Swendy.elsasser@arm.com# All rights reserved. 39243SN/A# 49243SN/A# Redistribution and use in source and binary forms, with or without 59243SN/A# modification, are permitted provided that the following conditions are 69243SN/A# met: redistributions of source code must retain the above copyright 79243SN/A# notice, this list of conditions and the following disclaimer; 89243SN/A# redistributions in binary form must reproduce the above copyright 99243SN/A# notice, this list of conditions and the following disclaimer in the 109243SN/A# documentation and/or other materials provided with the distribution; 119243SN/A# neither the name of the copyright holders nor the names of its 129243SN/A# contributors may be used to endorse or promote products derived from 139243SN/A# this software without specific prior written permission. 149831SN/A# 159831SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169831SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269243SN/A# 279243SN/A# Authors: Steve Reinhardt 289243SN/A 299243SN/Aimport m5 309243SN/Afrom m5.objects import * 319243SN/Afrom m5.defines import buildEnv 329243SN/Afrom m5.util import addToPath 339243SN/Aimport os, optparse, sys 349243SN/A 359243SN/Aif buildEnv['FULL_SYSTEM']: 369243SN/A panic("This script requires system-emulation mode (*_SE).") 379243SN/A 389243SN/A# Get paths we might need 399243SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 409243SN/Aconfig_root = os.path.dirname(config_path) 419243SN/Am5_root = os.path.dirname(config_root) 429967SN/AaddToPath(config_root+'/configs/common') 4310618SOmar.Naji@arm.comaddToPath(config_root+'/configs/ruby') 4411678Swendy.elsasser@arm.com 459243SN/Aimport Ruby 469243SN/A 4710146Sandreas.hansson@arm.comparser = optparse.OptionParser() 489356SN/A 4910146Sandreas.hansson@arm.com# 5010247Sandreas.hansson@arm.com# Add the ruby specific and protocol specific options 5110208Sandreas.hansson@arm.com# 529352SN/ARuby.define_options(parser) 5310146Sandreas.hansson@arm.com 549814SN/Aexecfile(os.path.join(config_root, "configs/common", "Options.py")) 559243SN/A 569243SN/A(options, args) = parser.parse_args() 5710432SOmar.Naji@arm.com 589243SN/A# 5910146Sandreas.hansson@arm.com# Set the default cache size and associativity to be very small to encourage 609243SN/A# races between requests and writebacks. 6110619Sandreas.hansson@arm.com# 629243SN/Aoptions.l1d_size="256B" 6310211Sandreas.hansson@arm.comoptions.l1i_size="256B" 6411678Swendy.elsasser@arm.comoptions.l2_size="512B" 6510618SOmar.Naji@arm.comoptions.l3_size="1kB" 6610489SOmar.Naji@arm.comoptions.l1d_assoc=2 679831SN/Aoptions.l1i_assoc=2 689831SN/Aoptions.l2_assoc=2 699831SN/Aoptions.l3_assoc=2 709831SN/A 719831SN/A# this is a uniprocessor only test 7210140SN/Aoptions.num_cpus = 1 7310646Sandreas.hansson@arm.com 749243SN/Acpu = TimingSimpleCPU(cpu_id=0) 7510394Swendy.elsasser@arm.comsystem = System(cpu = cpu, physmem = PhysicalMemory()) 7610394Swendy.elsasser@arm.com 779566SN/Asystem.ruby = Ruby.create_system(options, system) 789243SN/A 799243SN/Aassert(len(system.ruby.cpu_ruby_ports) == 1) 8010140SN/A 8110140SN/A# 8210147Sandreas.hansson@arm.com# Tie the cpu cache ports to the ruby cpu ports and 8310147Sandreas.hansson@arm.com# physmem, respectively 8410393Swendy.elsasser@arm.com# 8510394Swendy.elsasser@arm.comcpu.icache_port = system.ruby.cpu_ruby_ports[0].port 8610394Swendy.elsasser@arm.comcpu.dcache_port = system.ruby.cpu_ruby_ports[0].port 8711673SOmar.Naji@arm.com 8811673SOmar.Naji@arm.com# ----------------------- 899243SN/A# run simulation 909243SN/A# ----------------------- 9110141SN/A 929726SN/Aroot = Root(system = system) 939726SN/Aroot.system.mem_mode = 'timing' 9410618SOmar.Naji@arm.com 9510618SOmar.Naji@arm.com# Not much point in this being higher than the L1 latency 969243SN/Am5.ticks.setGlobalFrequency('1ns') 9710620Sandreas.hansson@arm.com