simple-timing-ruby.py revision 10120:f5ceb3c3edb6
112855Sgabeblack@google.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 212855Sgabeblack@google.com# All rights reserved. 312855Sgabeblack@google.com# 412855Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 512855Sgabeblack@google.com# modification, are permitted provided that the following conditions are 612855Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 712855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 812855Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 912855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 1012855Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 1112855Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 1212855Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 1312855Sgabeblack@google.com# this software without specific prior written permission. 1412855Sgabeblack@google.com# 1512855Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1612855Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1712855Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1812855Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1912855Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2012855Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2112855Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2212855Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2312855Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2412855Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2512855Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2612855Sgabeblack@google.com# 2712855Sgabeblack@google.com# Authors: Steve Reinhardt 2812855Sgabeblack@google.com 2912855Sgabeblack@google.comimport m5 3012855Sgabeblack@google.comfrom m5.objects import * 3112855Sgabeblack@google.comfrom m5.defines import buildEnv 3212855Sgabeblack@google.comfrom m5.util import addToPath 3312855Sgabeblack@google.comimport os, optparse, sys 3412855Sgabeblack@google.com 3512855Sgabeblack@google.com# Get paths we might need 3612855Sgabeblack@google.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 3712855Sgabeblack@google.comconfig_root = os.path.dirname(config_path) 3812855Sgabeblack@google.comaddToPath(config_root+'/configs/common') 3912855Sgabeblack@google.comaddToPath(config_root+'/configs/ruby') 4012855Sgabeblack@google.comaddToPath(config_root+'/configs/topologies') 4112855Sgabeblack@google.com 4212855Sgabeblack@google.comimport Ruby 4312855Sgabeblack@google.comimport Options 4412855Sgabeblack@google.com 4512855Sgabeblack@google.comparser = optparse.OptionParser() 4612855Sgabeblack@google.comOptions.addCommonOptions(parser) 4712855Sgabeblack@google.com 4812855Sgabeblack@google.com# Add the ruby specific and protocol specific options 4912855Sgabeblack@google.comRuby.define_options(parser) 5012855Sgabeblack@google.com 5112855Sgabeblack@google.com(options, args) = parser.parse_args() 5212855Sgabeblack@google.com 5312855Sgabeblack@google.com# 5412855Sgabeblack@google.com# Set the default cache size and associativity to be very small to encourage 5512855Sgabeblack@google.com# races between requests and writebacks. 5612855Sgabeblack@google.com# 5712855Sgabeblack@google.comoptions.l1d_size="256B" 5812855Sgabeblack@google.comoptions.l1i_size="256B" 5912855Sgabeblack@google.comoptions.l2_size="512B" 6012855Sgabeblack@google.comoptions.l3_size="1kB" 6112855Sgabeblack@google.comoptions.l1d_assoc=2 6212855Sgabeblack@google.comoptions.l1i_assoc=2 6312855Sgabeblack@google.comoptions.l2_assoc=2 6412855Sgabeblack@google.comoptions.l3_assoc=2 6512855Sgabeblack@google.com 6612855Sgabeblack@google.com# this is a uniprocessor only test 6712855Sgabeblack@google.comoptions.num_cpus = 1 6812855Sgabeblack@google.com 6912855Sgabeblack@google.comcpu = TimingSimpleCPU(cpu_id=0) 7012855Sgabeblack@google.comsystem = System(cpu = cpu, physmem = SimpleMemory(null = True)) 7112855Sgabeblack@google.com# Dummy voltage domain for all our clock domains 7212855Sgabeblack@google.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 7312855Sgabeblack@google.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 7412855Sgabeblack@google.com voltage_domain = system.voltage_domain) 7512855Sgabeblack@google.com 76# Create a seperate clock domain for components that should run at 77# CPUs frequency 78system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 79 voltage_domain = system.voltage_domain) 80 81system.mem_ranges = AddrRange('256MB') 82Ruby.create_system(options, system) 83 84# Create a separate clock for Ruby 85system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 86 voltage_domain = system.voltage_domain) 87 88assert(len(system.ruby._cpu_ports) == 1) 89 90# create the interrupt controller 91cpu.createInterruptController() 92 93# 94# Tie the cpu cache ports to the ruby cpu ports and 95# physmem, respectively 96# 97cpu.connectAllPorts(system.ruby._cpu_ports[0]) 98 99# ----------------------- 100# run simulation 101# ----------------------- 102 103root = Root(full_system = False, system = system) 104root.system.mem_mode = 'timing' 105 106# Not much point in this being higher than the L1 latency 107m5.ticks.setGlobalFrequency('1ns') 108