simple-timing-ruby.py revision 10117
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26166Ssteve.reinhardt@amd.com# All rights reserved. 36166Ssteve.reinhardt@amd.com# 46166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 56166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 66166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 76166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 86166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 96166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 106166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 116166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 126166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 136166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 146166Ssteve.reinhardt@amd.com# 156166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266166Ssteve.reinhardt@amd.com# 276166Ssteve.reinhardt@amd.com# Authors: Steve Reinhardt 286166Ssteve.reinhardt@amd.com 296166Ssteve.reinhardt@amd.comimport m5 306166Ssteve.reinhardt@amd.comfrom m5.objects import * 316928SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 326928SBrad.Beckmann@amd.comfrom m5.util import addToPath 336928SBrad.Beckmann@amd.comimport os, optparse, sys 346166Ssteve.reinhardt@amd.com 356928SBrad.Beckmann@amd.com# Get paths we might need 366928SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 376928SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 386928SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/common') 396928SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/ruby') 409113SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/topologies') 416928SBrad.Beckmann@amd.com 426928SBrad.Beckmann@amd.comimport Ruby 438920Snilay@cs.wisc.eduimport Options 446928SBrad.Beckmann@amd.com 456928SBrad.Beckmann@amd.comparser = optparse.OptionParser() 468920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 476928SBrad.Beckmann@amd.com 487570SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 497570SBrad.Beckmann@amd.comRuby.define_options(parser) 506928SBrad.Beckmann@amd.com 516928SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 526928SBrad.Beckmann@amd.com 537570SBrad.Beckmann@amd.com# 547570SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 557570SBrad.Beckmann@amd.com# races between requests and writebacks. 567570SBrad.Beckmann@amd.com# 577570SBrad.Beckmann@amd.comoptions.l1d_size="256B" 587570SBrad.Beckmann@amd.comoptions.l1i_size="256B" 597570SBrad.Beckmann@amd.comoptions.l2_size="512B" 607570SBrad.Beckmann@amd.comoptions.l3_size="1kB" 617570SBrad.Beckmann@amd.comoptions.l1d_assoc=2 627570SBrad.Beckmann@amd.comoptions.l1i_assoc=2 637570SBrad.Beckmann@amd.comoptions.l2_assoc=2 647570SBrad.Beckmann@amd.comoptions.l3_assoc=2 657570SBrad.Beckmann@amd.com 666928SBrad.Beckmann@amd.com# this is a uniprocessor only test 676928SBrad.Beckmann@amd.comoptions.num_cpus = 1 686289Snate@binkert.org 696166Ssteve.reinhardt@amd.comcpu = TimingSimpleCPU(cpu_id=0) 709827Sakash.bagdia@arm.comsystem = System(cpu = cpu, physmem = SimpleMemory(null = True)) 719827Sakash.bagdia@arm.com# Dummy voltage domain for all our clock domains 729827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 739827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 749827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 759793Sakash.bagdia@arm.com 769793Sakash.bagdia@arm.com# Create a seperate clock domain for components that should run at 779793Sakash.bagdia@arm.com# CPUs frequency 789827Sakash.bagdia@arm.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 799827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 806928SBrad.Beckmann@amd.com 819826Sandreas.hansson@arm.comsystem.mem_ranges = AddrRange('256MB') 8210117Snilay@cs.wisc.eduRuby.create_system(options, system) 836928SBrad.Beckmann@amd.com 849793Sakash.bagdia@arm.com# Create a separate clock for Ruby 859827Sakash.bagdia@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 869827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 879793Sakash.bagdia@arm.com 888322Ssteve.reinhardt@amd.comassert(len(system.ruby._cpu_ruby_ports) == 1) 896928SBrad.Beckmann@amd.com 908876Sandreas.hansson@arm.com# create the interrupt controller 918876Sandreas.hansson@arm.comcpu.createInterruptController() 928876Sandreas.hansson@arm.com 936928SBrad.Beckmann@amd.com# 946928SBrad.Beckmann@amd.com# Tie the cpu cache ports to the ruby cpu ports and 956928SBrad.Beckmann@amd.com# physmem, respectively 966928SBrad.Beckmann@amd.com# 978744Sgblack@eecs.umich.educpu.connectAllPorts(system.ruby._cpu_ruby_ports[0]) 986928SBrad.Beckmann@amd.com 996928SBrad.Beckmann@amd.com# ----------------------- 1006928SBrad.Beckmann@amd.com# run simulation 1016928SBrad.Beckmann@amd.com# ----------------------- 1026166Ssteve.reinhardt@amd.com 1038801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 1046928SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing' 1056928SBrad.Beckmann@amd.com 1066928SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency 1076928SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns') 108