simple-timing-mp.py revision 9288:3d6da8559605
14120Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
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264120Sgblack@eecs.umich.edu#
274120Sgblack@eecs.umich.edu# Authors: Ron Dreslinski
284120Sgblack@eecs.umich.edu
294120Sgblack@eecs.umich.eduimport m5
304120Sgblack@eecs.umich.edufrom m5.objects import *
314120Sgblack@eecs.umich.edu
324120Sgblack@eecs.umich.edu# --------------------
334120Sgblack@eecs.umich.edu# Base L1 Cache
344120Sgblack@eecs.umich.edu# ====================
354120Sgblack@eecs.umich.edu
364120Sgblack@eecs.umich.educlass L1(BaseCache):
374120Sgblack@eecs.umich.edu    hit_latency = 2
384120Sgblack@eecs.umich.edu    response_latency = 2
394120Sgblack@eecs.umich.edu    block_size = 64
404120Sgblack@eecs.umich.edu    mshrs = 4
414120Sgblack@eecs.umich.edu    tgts_per_mshr = 8
424120Sgblack@eecs.umich.edu    is_top_level = True
434120Sgblack@eecs.umich.edu
444120Sgblack@eecs.umich.edu# ----------------------
454120Sgblack@eecs.umich.edu# Base L2 Cache
464120Sgblack@eecs.umich.edu# ----------------------
474120Sgblack@eecs.umich.edu
484120Sgblack@eecs.umich.educlass L2(BaseCache):
494120Sgblack@eecs.umich.edu    block_size = 64
504120Sgblack@eecs.umich.edu    hit_latency = 20
514120Sgblack@eecs.umich.edu    response_latency = 20
524120Sgblack@eecs.umich.edu    mshrs = 92
534120Sgblack@eecs.umich.edu    tgts_per_mshr = 16
544120Sgblack@eecs.umich.edu    write_buffers = 8
554120Sgblack@eecs.umich.edu
564120Sgblack@eecs.umich.edunb_cores = 4
574120Sgblack@eecs.umich.educpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
584120Sgblack@eecs.umich.edu
594120Sgblack@eecs.umich.edu# system simulated
604120Sgblack@eecs.umich.edusystem = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
615124Sgblack@eecs.umich.edu
625237Sgblack@eecs.umich.edu# l2cache & bus
635236Sgblack@eecs.umich.edusystem.toL2Bus = CoherentBus(clock = '2GHz')
645124Sgblack@eecs.umich.edusystem.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
655124Sgblack@eecs.umich.edusystem.l2c.cpu_side = system.toL2Bus.master
665124Sgblack@eecs.umich.edu
675086Sgblack@eecs.umich.edu# connect l2c to membus
685236Sgblack@eecs.umich.edusystem.l2c.mem_side = system.membus.slave
695086Sgblack@eecs.umich.edu
705086Sgblack@eecs.umich.edu# add L1 caches
715086Sgblack@eecs.umich.edufor cpu in cpus:
725086Sgblack@eecs.umich.edu    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
735086Sgblack@eecs.umich.edu                                L1(size = '32kB', assoc = 4))
745086Sgblack@eecs.umich.edu    # create the interrupt controller
755086Sgblack@eecs.umich.edu    cpu.createInterruptController()
765086Sgblack@eecs.umich.edu    # connect cpu level-1 caches to shared level-2 cache
775086Sgblack@eecs.umich.edu    cpu.connectAllPorts(system.toL2Bus, system.membus)
785086Sgblack@eecs.umich.edu    cpu.clock = '2GHz'
795086Sgblack@eecs.umich.edu
805118Sgblack@eecs.umich.edusystem.system_port = system.membus.slave
815118Sgblack@eecs.umich.edu
825236Sgblack@eecs.umich.edu# connect memory to membus
835236Sgblack@eecs.umich.edusystem.physmem.port = system.membus.master
845236Sgblack@eecs.umich.edu
855086Sgblack@eecs.umich.edu
865124Sgblack@eecs.umich.edu# -----------------------
875124Sgblack@eecs.umich.edu# run simulation
885124Sgblack@eecs.umich.edu# -----------------------
895236Sgblack@eecs.umich.edu
905236Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system )
915236Sgblack@eecs.umich.eduroot.system.mem_mode = 'timing'
925237Sgblack@eecs.umich.edu