simple-timing-mp.py revision 6978:ab05e20dc4a7
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31 32# -------------------- 33# Base L1 Cache 34# ==================== 35 36class L1(BaseCache): 37 latency = '1ns' 38 block_size = 64 39 mshrs = 4 40 tgts_per_mshr = 8 41 42# ---------------------- 43# Base L2 Cache 44# ---------------------- 45 46class L2(BaseCache): 47 block_size = 64 48 latency = '10ns' 49 mshrs = 92 50 tgts_per_mshr = 16 51 write_buffers = 8 52 53nb_cores = 4 54cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 55 56# system simulated 57system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 58Bus()) 59 60# l2cache & bus 61system.toL2Bus = Bus() 62system.l2c = L2(size='4MB', assoc=8) 63system.l2c.cpu_side = system.toL2Bus.port 64system.l2c.num_cpus = nb_cores 65 66# connect l2c to membus 67system.l2c.mem_side = system.membus.port 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) 73 # connect cpu level-1 caches to shared level-2 cache 74 cpu.connectMemPorts(system.toL2Bus) 75 cpu.clock = '2GHz' 76 77# connect memory to membus 78system.physmem.port = system.membus.port 79 80 81# ----------------------- 82# run simulation 83# ----------------------- 84 85root = Root( system = system ) 86root.system.mem_mode = 'timing' 87