simple-atomic-mp.py revision 9324:8650f0c53db5
111308Santhony.gutierrez@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 211308Santhony.gutierrez@amd.com# All rights reserved. 311308Santhony.gutierrez@amd.com# 411308Santhony.gutierrez@amd.com# Redistribution and use in source and binary forms, with or without 511308Santhony.gutierrez@amd.com# modification, are permitted provided that the following conditions are 611308Santhony.gutierrez@amd.com# met: redistributions of source code must retain the above copyright 711308Santhony.gutierrez@amd.com# notice, this list of conditions and the following disclaimer; 811308Santhony.gutierrez@amd.com# redistributions in binary form must reproduce the above copyright 911308Santhony.gutierrez@amd.com# notice, this list of conditions and the following disclaimer in the 1011308Santhony.gutierrez@amd.com# documentation and/or other materials provided with the distribution; 1111308Santhony.gutierrez@amd.com# neither the name of the copyright holders nor the names of its 1211308Santhony.gutierrez@amd.com# contributors may be used to endorse or promote products derived from 1311308Santhony.gutierrez@amd.com# this software without specific prior written permission. 1411308Santhony.gutierrez@amd.com# 1511308Santhony.gutierrez@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1611308Santhony.gutierrez@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1711308Santhony.gutierrez@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1811308Santhony.gutierrez@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1911308Santhony.gutierrez@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2011308Santhony.gutierrez@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2111308Santhony.gutierrez@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2211308Santhony.gutierrez@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2311308Santhony.gutierrez@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2411308Santhony.gutierrez@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2511308Santhony.gutierrez@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2611308Santhony.gutierrez@amd.com# 2711308Santhony.gutierrez@amd.com# Authors: Ron Dreslinski 2811308Santhony.gutierrez@amd.com 2911308Santhony.gutierrez@amd.comimport m5 3011308Santhony.gutierrez@amd.comfrom m5.objects import * 3111308Santhony.gutierrez@amd.comm5.util.addToPath('../configs/common') 3211308Santhony.gutierrez@amd.comfrom Caches import * 3311308Santhony.gutierrez@amd.com 3411308Santhony.gutierrez@amd.comnb_cores = 4 3511308Santhony.gutierrez@amd.comcpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 3611308Santhony.gutierrez@amd.com 3711308Santhony.gutierrez@amd.com# system simulated 3811308Santhony.gutierrez@amd.comsystem = System(cpu = cpus, 3911308Santhony.gutierrez@amd.com physmem = SimpleMemory(range = AddrRange('1024MB')), 4011308Santhony.gutierrez@amd.com membus = CoherentBus()) 4111308Santhony.gutierrez@amd.com 4211308Santhony.gutierrez@amd.com# l2cache & bus 4311308Santhony.gutierrez@amd.comsystem.toL2Bus = CoherentBus(clock = '2GHz') 4411308Santhony.gutierrez@amd.comsystem.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 4511308Santhony.gutierrez@amd.comsystem.l2c.cpu_side = system.toL2Bus.master 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.com# connect l2c to membus 4811308Santhony.gutierrez@amd.comsystem.l2c.mem_side = system.membus.slave 4911308Santhony.gutierrez@amd.com 5011308Santhony.gutierrez@amd.com# add L1 caches 5111308Santhony.gutierrez@amd.comfor cpu in cpus: 5211308Santhony.gutierrez@amd.com cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), 5311308Santhony.gutierrez@amd.com L1Cache(size = '32kB', assoc = 4)) 5411308Santhony.gutierrez@amd.com # create the interrupt controller 5511641Salexandru.dutu@amd.com cpu.createInterruptController() 5611641Salexandru.dutu@amd.com # connect cpu level-1 caches to shared level-2 cache 5711641Salexandru.dutu@amd.com cpu.connectAllPorts(system.toL2Bus, system.membus) 5811641Salexandru.dutu@amd.com cpu.clock = '2GHz' 5911641Salexandru.dutu@amd.com 6011641Salexandru.dutu@amd.com# connect memory to membus 6111641Salexandru.dutu@amd.comsystem.physmem.port = system.membus.master 6211641Salexandru.dutu@amd.com 6311641Salexandru.dutu@amd.com# connect system port to membus 6411641Salexandru.dutu@amd.comsystem.system_port = system.membus.slave 6511641Salexandru.dutu@amd.com 6611641Salexandru.dutu@amd.com# ----------------------- 6711641Salexandru.dutu@amd.com# run simulation 6811641Salexandru.dutu@amd.com# ----------------------- 6911641Salexandru.dutu@amd.com 7011641Salexandru.dutu@amd.comroot = Root( full_system = False, system = system ) 7111641Salexandru.dutu@amd.comroot.system.mem_mode = 'atomic' 7211641Salexandru.dutu@amd.com