simple-atomic-mp.py revision 9324:8650f0c53db5 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34nb_cores = 4
35cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus,
39                physmem = SimpleMemory(range = AddrRange('1024MB')),
40                membus = CoherentBus())
41
42# l2cache & bus
43system.toL2Bus = CoherentBus(clock = '2GHz')
44system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
45system.l2c.cpu_side = system.toL2Bus.master
46
47# connect l2c to membus
48system.l2c.mem_side = system.membus.slave
49
50# add L1 caches
51for cpu in cpus:
52    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
53                                L1Cache(size = '32kB', assoc = 4))
54    # create the interrupt controller
55    cpu.createInterruptController()
56    # connect cpu level-1 caches to shared level-2 cache
57    cpu.connectAllPorts(system.toL2Bus, system.membus)
58    cpu.clock = '2GHz'
59
60# connect memory to membus
61system.physmem.port = system.membus.master
62
63# connect system port to membus
64system.system_port = system.membus.slave
65
66# -----------------------
67# run simulation
68# -----------------------
69
70root = Root( full_system = False, system = system )
71root.system.mem_mode = 'atomic'
72