simple-atomic-mp.py revision 9036:6385cf85bf12 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37    latency = '1ns'
38    block_size = 64
39    mshrs = 4
40    tgts_per_mshr = 8
41    is_top_level = True
42
43# ----------------------
44# Base L2 Cache
45# ----------------------
46
47class L2(BaseCache):
48    block_size = 64
49    latency = '10ns'
50    mshrs = 92
51    tgts_per_mshr = 16
52    write_buffers = 8
53
54nb_cores = 4
55cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
56
57# system simulated
58system = System(cpu = cpus,
59                physmem = SimpleMemory(range = AddrRange('1024MB')),
60                membus = CoherentBus())
61
62# l2cache & bus
63system.toL2Bus = CoherentBus()
64system.l2c = L2(size='4MB', assoc=8)
65system.l2c.cpu_side = system.toL2Bus.master
66
67# connect l2c to membus
68system.l2c.mem_side = system.membus.slave
69
70# add L1 caches
71for cpu in cpus:
72    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
73                                L1(size = '32kB', assoc = 4))
74    # create the interrupt controller
75    cpu.createInterruptController()
76    # connect cpu level-1 caches to shared level-2 cache
77    cpu.connectAllPorts(system.toL2Bus, system.membus)
78    cpu.clock = '2GHz'
79
80# connect memory to membus
81system.physmem.port = system.membus.master
82
83# connect system port to membus
84system.system_port = system.membus.slave
85
86# -----------------------
87# run simulation
88# -----------------------
89
90root = Root( full_system = False, system = system )
91root.system.mem_mode = 'atomic'
92