simple-atomic-mp.py revision 8876:44f8e7bb7fdf
12381SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22381SN/A# All rights reserved. 32381SN/A# 42381SN/A# Redistribution and use in source and binary forms, with or without 52381SN/A# modification, are permitted provided that the following conditions are 62381SN/A# met: redistributions of source code must retain the above copyright 72381SN/A# notice, this list of conditions and the following disclaimer; 82381SN/A# redistributions in binary form must reproduce the above copyright 92381SN/A# notice, this list of conditions and the following disclaimer in the 102381SN/A# documentation and/or other materials provided with the distribution; 112381SN/A# neither the name of the copyright holders nor the names of its 122381SN/A# contributors may be used to endorse or promote products derived from 132381SN/A# this software without specific prior written permission. 142381SN/A# 152381SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162381SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172381SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182381SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192381SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202381SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212381SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222381SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232381SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242381SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252381SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262381SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduimport m5 302665Ssaidi@eecs.umich.edufrom m5.objects import * 312381SN/A 322381SN/A# -------------------- 332381SN/A# Base L1 Cache 342982Sstever@eecs.umich.edu# ==================== 352982Sstever@eecs.umich.edu 362381SN/Aclass L1(BaseCache): 372381SN/A latency = '1ns' 382381SN/A block_size = 64 392381SN/A mshrs = 4 402381SN/A tgts_per_mshr = 8 412381SN/A is_top_level = True 425735Snate@binkert.org 435735Snate@binkert.org# ---------------------- 444610Ssaidi@eecs.umich.edu# Base L2 Cache 455735Snate@binkert.org# ---------------------- 465744Sgblack@eecs.umich.edu 476214Snate@binkert.orgclass L2(BaseCache): 484167Sbinkertn@umich.edu block_size = 64 492394SN/A latency = '10ns' 502394SN/A mshrs = 92 512394SN/A tgts_per_mshr = 16 522394SN/A write_buffers = 8 532394SN/A 544610Ssaidi@eecs.umich.edunb_cores = 4 552381SN/Acpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 565735Snate@binkert.org 575735Snate@binkert.org# system simulated 585735Snate@binkert.orgsystem = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus = 595735Snate@binkert.orgBus()) 605735Snate@binkert.org 615735Snate@binkert.org# l2cache & bus 626133Ssteve.reinhardt@amd.comsystem.toL2Bus = Bus() 636133Ssteve.reinhardt@amd.comsystem.l2c = L2(size='4MB', assoc=8) 645735Snate@binkert.orgsystem.l2c.cpu_side = system.toL2Bus.master 655735Snate@binkert.org 665735Snate@binkert.org# connect l2c to membus 675735Snate@binkert.orgsystem.l2c.mem_side = system.membus.slave 685735Snate@binkert.org 695735Snate@binkert.org# add L1 caches 705735Snate@binkert.orgfor cpu in cpus: 715735Snate@binkert.org cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 726133Ssteve.reinhardt@amd.com L1(size = '32kB', assoc = 4)) 736133Ssteve.reinhardt@amd.com # create the interrupt controller 746133Ssteve.reinhardt@amd.com cpu.createInterruptController() 755735Snate@binkert.org # connect cpu level-1 caches to shared level-2 cache 766133Ssteve.reinhardt@amd.com cpu.connectAllPorts(system.toL2Bus, system.membus) 776133Ssteve.reinhardt@amd.com cpu.clock = '2GHz' 786133Ssteve.reinhardt@amd.com 796133Ssteve.reinhardt@amd.com# connect memory to membus 806133Ssteve.reinhardt@amd.comsystem.physmem.port = system.membus.master 815890Sgblack@eecs.umich.edu 826133Ssteve.reinhardt@amd.com# connect system port to membus 836103Sgblack@eecs.umich.edusystem.system_port = system.membus.slave 846103Sgblack@eecs.umich.edu 856103Sgblack@eecs.umich.edu# ----------------------- 866103Sgblack@eecs.umich.edu# run simulation 876103Sgblack@eecs.umich.edu# ----------------------- 886103Sgblack@eecs.umich.edu 896133Ssteve.reinhardt@amd.comroot = Root( full_system = False, system = system ) 906133Ssteve.reinhardt@amd.comroot.system.mem_mode = 'atomic' 916133Ssteve.reinhardt@amd.com