simple-atomic-mp.py revision 3134:cf578b0dd70d
1955SN/A# Copyright (c) 2006 The Regents of The University of Michigan 2955SN/A# All rights reserved. 39812Sandreas.hansson@arm.com# 49812Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 59812Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 69812Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 79812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 89812Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 99812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 109812Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 119812Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 129812Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 139812Sandreas.hansson@arm.com# this software without specific prior written permission. 149812Sandreas.hansson@arm.com# 157816Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165871Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 171762SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26955SN/A# 27955SN/A# Authors: Ron Dreslinski 28955SN/A 29955SN/Aimport m5 30955SN/Afrom m5.objects import * 31955SN/A 32955SN/A# -------------------- 33955SN/A# Base L1 Cache 34955SN/A# ==================== 35955SN/A 36955SN/Aclass L1(BaseCache): 37955SN/A latency = 1 38955SN/A block_size = 64 39955SN/A mshrs = 4 40955SN/A tgts_per_mshr = 8 41955SN/A protocol = CoherenceProtocol(protocol='moesi') 422665Ssaidi@eecs.umich.edu 432665Ssaidi@eecs.umich.edu# ---------------------- 445863Snate@binkert.org# Base L2 Cache 45955SN/A# ---------------------- 46955SN/A 47955SN/Aclass L2(BaseCache): 48955SN/A block_size = 64 49955SN/A latency = 100 508878Ssteve.reinhardt@amd.com mshrs = 92 512632Sstever@eecs.umich.edu tgts_per_mshr = 16 528878Ssteve.reinhardt@amd.com write_buffers = 8 532632Sstever@eecs.umich.edu 54955SN/Anb_cores = 4 558878Ssteve.reinhardt@amd.comcpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ] 562632Sstever@eecs.umich.edu 572761Sstever@eecs.umich.edu# system simulated 582632Sstever@eecs.umich.edusystem = System(cpu = cpus, physmem = PhysicalMemory(), membus = 592632Sstever@eecs.umich.eduBus()) 602632Sstever@eecs.umich.edu 612761Sstever@eecs.umich.edu# l2cache & bus 622761Sstever@eecs.umich.edusystem.toL2Bus = Bus() 632761Sstever@eecs.umich.edusystem.l2c = L2(size='4MB', assoc=8) 648878Ssteve.reinhardt@amd.comsystem.l2c.cpu_side = system.toL2Bus.port 658878Ssteve.reinhardt@amd.com 662761Sstever@eecs.umich.edu# connect l2c to membus 672761Sstever@eecs.umich.edusystem.l2c.mem_side = system.membus.port 682761Sstever@eecs.umich.edu 692761Sstever@eecs.umich.edu# add L1 caches 702761Sstever@eecs.umich.edufor cpu in cpus: 718878Ssteve.reinhardt@amd.com cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 728878Ssteve.reinhardt@amd.com L1(size = '32kB', assoc = 4)) 732632Sstever@eecs.umich.edu cpu.mem = cpu.dcache 742632Sstever@eecs.umich.edu # connect cpu level-1 caches to shared level-2 cache 758878Ssteve.reinhardt@amd.com cpu.connectMemPorts(system.toL2Bus) 768878Ssteve.reinhardt@amd.com 772632Sstever@eecs.umich.edu# connect memory to membus 78955SN/Asystem.physmem.port = system.membus.port 79955SN/A 80955SN/A 815863Snate@binkert.org# ----------------------- 825863Snate@binkert.org# run simulation 835863Snate@binkert.org# ----------------------- 845863Snate@binkert.org 855863Snate@binkert.orgroot = Root( system = system ) 865863Snate@binkert.orgroot.system.mem_mode = 'atomic' 875863Snate@binkert.org