simple-atomic-mp.py revision 3134:cf578b0dd70d 
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37    latency = 1
38    block_size = 64
39    mshrs = 4
40    tgts_per_mshr = 8
41    protocol = CoherenceProtocol(protocol='moesi')
42
43# ----------------------
44# Base L2 Cache
45# ----------------------
46
47class L2(BaseCache):
48    block_size = 64
49    latency = 100
50    mshrs = 92
51    tgts_per_mshr = 16
52    write_buffers = 8
53
54nb_cores = 4
55cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ]
56
57# system simulated
58system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
59Bus())
60
61# l2cache & bus
62system.toL2Bus = Bus()
63system.l2c = L2(size='4MB', assoc=8)
64system.l2c.cpu_side = system.toL2Bus.port
65
66# connect l2c to membus
67system.l2c.mem_side = system.membus.port
68
69# add L1 caches
70for cpu in cpus:
71    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
72                                L1(size = '32kB', assoc = 4))
73    cpu.mem = cpu.dcache
74    # connect cpu level-1 caches to shared level-2 cache
75    cpu.connectMemPorts(system.toL2Bus)
76
77# connect memory to membus
78system.physmem.port = system.membus.port
79
80
81# -----------------------
82# run simulation
83# -----------------------
84
85root = Root( system = system )
86root.system.mem_mode = 'atomic'
87