simple-atomic-mp.py revision 3134:cf578b0dd70d
112272SGeoffrey.Blake@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 26757SAli.Saidi@ARM.com# All rights reserved. 36757SAli.Saidi@ARM.com# 47585SAli.Saidi@arm.com# Redistribution and use in source and binary forms, with or without 57585SAli.Saidi@arm.com# modification, are permitted provided that the following conditions are 67585SAli.Saidi@arm.com# met: redistributions of source code must retain the above copyright 77585SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer; 87585SAli.Saidi@arm.com# redistributions in binary form must reproduce the above copyright 97585SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer in the 107585SAli.Saidi@arm.com# documentation and/or other materials provided with the distribution; 117585SAli.Saidi@arm.com# neither the name of the copyright holders nor the names of its 127585SAli.Saidi@arm.com# contributors may be used to endorse or promote products derived from 136757SAli.Saidi@ARM.com# this software without specific prior written permission. 146757SAli.Saidi@ARM.com# 156757SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166757SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176757SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186757SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196757SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206757SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216757SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226757SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236757SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246757SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256757SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266757SAli.Saidi@ARM.com# 276757SAli.Saidi@ARM.com# Authors: Ron Dreslinski 286757SAli.Saidi@ARM.com 296757SAli.Saidi@ARM.comimport m5 306757SAli.Saidi@ARM.comfrom m5.objects import * 316757SAli.Saidi@ARM.com 326757SAli.Saidi@ARM.com# -------------------- 336757SAli.Saidi@ARM.com# Base L1 Cache 346757SAli.Saidi@ARM.com# ==================== 356757SAli.Saidi@ARM.com 366757SAli.Saidi@ARM.comclass L1(BaseCache): 376757SAli.Saidi@ARM.com latency = 1 386757SAli.Saidi@ARM.com block_size = 64 3911988Sandreas.sandberg@arm.com mshrs = 4 406757SAli.Saidi@ARM.com tgts_per_mshr = 8 416757SAli.Saidi@ARM.com protocol = CoherenceProtocol(protocol='moesi') 426757SAli.Saidi@ARM.com 437585SAli.Saidi@arm.com# ---------------------- 4411238Sandreas.sandberg@arm.com# Base L2 Cache 4511238Sandreas.sandberg@arm.com# ---------------------- 4611238Sandreas.sandberg@arm.com 4711238Sandreas.sandberg@arm.comclass L2(BaseCache): 4811238Sandreas.sandberg@arm.com block_size = 64 4911238Sandreas.sandberg@arm.com latency = 100 5011238Sandreas.sandberg@arm.com mshrs = 92 517585SAli.Saidi@arm.com tgts_per_mshr = 16 526757SAli.Saidi@ARM.com write_buffers = 8 536757SAli.Saidi@ARM.com 549338SAndreas.Sandberg@arm.comnb_cores = 4 559050Schander.sudanthi@arm.comcpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ] 5611234Sandreas.sandberg@arm.com 5711234Sandreas.sandberg@arm.com# system simulated 5811234Sandreas.sandberg@arm.comsystem = System(cpu = cpus, physmem = PhysicalMemory(), membus = 5911234Sandreas.sandberg@arm.comBus()) 608286SAli.Saidi@ARM.com 618286SAli.Saidi@ARM.com# l2cache & bus 6210037SARM gem5 Developerssystem.toL2Bus = Bus() 6310037SARM gem5 Developerssystem.l2c = L2(size='4MB', assoc=8) 6410037SARM gem5 Developerssystem.l2c.cpu_side = system.toL2Bus.port 6510037SARM gem5 Developers 6611506Sandreas.sandberg@arm.com# connect l2c to membus 6710037SARM gem5 Developerssystem.l2c.mem_side = system.membus.port 6810037SARM gem5 Developers 6910037SARM gem5 Developers# add L1 caches 7010317Smitch.hayenga@arm.comfor cpu in cpus: 7110037SARM gem5 Developers cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 7210037SARM gem5 Developers L1(size = '32kB', assoc = 4)) 7310037SARM gem5 Developers cpu.mem = cpu.dcache 7410037SARM gem5 Developers # connect cpu level-1 caches to shared level-2 cache 7510037SARM gem5 Developers cpu.connectMemPorts(system.toL2Bus) 7610037SARM gem5 Developers 776757SAli.Saidi@ARM.com# connect memory to membus 7812005Sandreas.sandberg@arm.comsystem.physmem.port = system.membus.port 7912005Sandreas.sandberg@arm.com 8012005Sandreas.sandberg@arm.com 8112005Sandreas.sandberg@arm.com# ----------------------- 8210810Sbr@bsdpad.com# run simulation 8310810Sbr@bsdpad.com# ----------------------- 8410810Sbr@bsdpad.com 8512153Sandreas.sandberg@arm.comroot = Root( system = system ) 867585SAli.Saidi@arm.comroot.system.mem_mode = 'atomic' 8710037SARM gem5 Developers