rubytest-ruby.py revision 9826:014ff1fbff6d
12817Sksewell@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 22817Sksewell@umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 32817Sksewell@umich.edu# All rights reserved. 42817Sksewell@umich.edu# 52817Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu# modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu# this software without specific prior written permission. 152817Sksewell@umich.edu# 162817Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu# 282817Sksewell@umich.edu# Authors: Ron Dreslinski 292817Sksewell@umich.edu# Brad Beckmann 302817Sksewell@umich.edu 312817Sksewell@umich.eduimport m5 322817Sksewell@umich.edufrom m5.objects import * 332817Sksewell@umich.edufrom m5.defines import buildEnv 346658Snate@binkert.orgfrom m5.util import addToPath 352935Sksewell@umich.eduimport os, optparse, sys 362817Sksewell@umich.edu 372817Sksewell@umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 382834Sksewell@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 392834Sksewell@umich.educonfig_root = os.path.dirname(config_path) 402834Sksewell@umich.edum5_root = os.path.dirname(config_root) 412834Sksewell@umich.eduaddToPath(config_root+'/configs/common') 422834Sksewell@umich.eduaddToPath(config_root+'/configs/ruby') 432834Sksewell@umich.eduaddToPath(config_root+'/configs/topologies') 442834Sksewell@umich.edu 452817Sksewell@umich.eduimport Ruby 462817Sksewell@umich.eduimport Options 472817Sksewell@umich.edu 482817Sksewell@umich.eduparser = optparse.OptionParser() 492817Sksewell@umich.eduOptions.addCommonOptions(parser) 502817Sksewell@umich.edu 512817Sksewell@umich.edu# Add the ruby specific and protocol specific options 522817Sksewell@umich.eduRuby.define_options(parser) 532817Sksewell@umich.edu 542817Sksewell@umich.edu(options, args) = parser.parse_args() 552817Sksewell@umich.edu 562817Sksewell@umich.edu# 572817Sksewell@umich.edu# Set the default cache size and associativity to be very small to encourage 582817Sksewell@umich.edu# races between requests and writebacks. 592817Sksewell@umich.edu# 602817Sksewell@umich.eduoptions.l1d_size="256B" 612817Sksewell@umich.eduoptions.l1i_size="256B" 622817Sksewell@umich.eduoptions.l2_size="512B" 632817Sksewell@umich.eduoptions.l3_size="1kB" 642817Sksewell@umich.eduoptions.l1d_assoc=2 652817Sksewell@umich.eduoptions.l1i_assoc=2 662817Sksewell@umich.eduoptions.l2_assoc=2 672817Sksewell@umich.eduoptions.l3_assoc=2 682817Sksewell@umich.edu 692817Sksewell@umich.edu# Turn on flush check for the hammer protocol 703784Sgblack@eecs.umich.educheck_flush = False 716022Sgblack@eecs.umich.eduif buildEnv['PROTOCOL'] == 'MOESI_hammer': 723784Sgblack@eecs.umich.edu check_flush = True 733784Sgblack@eecs.umich.edu 746022Sgblack@eecs.umich.edu# 753784Sgblack@eecs.umich.edu# create the tester and system, including ruby 762817Sksewell@umich.edu# 772817Sksewell@umich.edutester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 782817Sksewell@umich.edu wakeup_frequency = 10, num_cpus = options.num_cpus) 792817Sksewell@umich.edu 805712Shsul@eecs.umich.edusystem = System(tester = tester, physmem = SimpleMemory(null = True), 812817Sksewell@umich.edu clk_domain = SrcClockDomain(clock = options.sys_clock)) 825714Shsul@eecs.umich.edu 835714Shsul@eecs.umich.edusystem.mem_ranges = AddrRange('256MB') 845714Shsul@eecs.umich.edu 855714Shsul@eecs.umich.eduRuby.create_system(options, system) 865715Shsul@eecs.umich.edu 875715Shsul@eecs.umich.edu# Create a separate clock domain for Ruby 885715Shsul@eecs.umich.edusystem.ruby.clk_domain = SrcClockDomain(clock = '1GHz') 895715Shsul@eecs.umich.edu 902817Sksewell@umich.eduassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 912817Sksewell@umich.edu 922817Sksewell@umich.edu# 935803Snate@binkert.org# The tester is most effective when randomization is turned on and 942817Sksewell@umich.edu# artifical delay is randomly inserted on messages 952817Sksewell@umich.edu# 962817Sksewell@umich.edusystem.ruby.randomization = True 972817Sksewell@umich.edu 983548Sgblack@eecs.umich.edufor ruby_port in system.ruby._cpu_ruby_ports: 992817Sksewell@umich.edu # 1002817Sksewell@umich.edu # Tie the ruby tester ports to the ruby cpu read and write ports 1012817Sksewell@umich.edu # 1022817Sksewell@umich.edu if ruby_port.support_data_reqs: 1035499Ssaidi@eecs.umich.edu tester.cpuDataPort = ruby_port.slave 1043675Sktlim@umich.edu if ruby_port.support_inst_reqs: 1055497Ssaidi@eecs.umich.edu tester.cpuInstPort = ruby_port.slave 1062817Sksewell@umich.edu 1072817Sksewell@umich.edu # 1082817Sksewell@umich.edu # Tell the sequencer this is the ruby tester so that it 1092817Sksewell@umich.edu # copies the subblock back to the checker 1102817Sksewell@umich.edu # 1112817Sksewell@umich.edu ruby_port.using_ruby_tester = True 1122817Sksewell@umich.edu 1132817Sksewell@umich.edu# ----------------------- 1142817Sksewell@umich.edu# run simulation 1152817Sksewell@umich.edu# ----------------------- 1162817Sksewell@umich.edu 1172817Sksewell@umich.eduroot = Root(full_system = False, system = system ) 1182817Sksewell@umich.eduroot.system.mem_mode = 'timing' 1192817Sksewell@umich.edu 1202817Sksewell@umich.edu# Not much point in this being higher than the L1 latency 1212817Sksewell@umich.edum5.ticks.setGlobalFrequency('1ns') 1222817Sksewell@umich.edu