rubytest-ruby.py revision 8940
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36 37# Get paths we might need. It's expected this file is in m5/configs/example. 38config_path = os.path.dirname(os.path.abspath(__file__)) 39config_root = os.path.dirname(config_path) 40m5_root = os.path.dirname(config_root) 41addToPath(config_root+'/configs/common') 42addToPath(config_root+'/configs/ruby') 43 44import Ruby 45import Options 46 47parser = optparse.OptionParser() 48Options.addCommonOptions(parser) 49 50# Add the ruby specific and protocol specific options 51Ruby.define_options(parser) 52 53(options, args) = parser.parse_args() 54 55# 56# Set the default cache size and associativity to be very small to encourage 57# races between requests and writebacks. 58# 59options.l1d_size="256B" 60options.l1i_size="256B" 61options.l2_size="512B" 62options.l3_size="1kB" 63options.l1d_assoc=2 64options.l1i_assoc=2 65options.l2_assoc=2 66options.l3_assoc=2 67 68# Turn on flush check for the hammer protocol 69check_flush = False 70if buildEnv['PROTOCOL'] == 'MOESI_hammer': 71 check_flush = True 72 73# 74# create the tester and system, including ruby 75# 76tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 77 wakeup_frequency = 10, num_cpus = options.num_cpus) 78 79system = System(tester = tester, physmem = SimpleMemory()) 80 81Ruby.create_system(options, system) 82 83assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 84 85# 86# The tester is most effective when randomization is turned on and 87# artifical delay is randomly inserted on messages 88# 89system.ruby.randomization = True 90 91for ruby_port in system.ruby._cpu_ruby_ports: 92 # 93 # Tie the ruby tester ports to the ruby cpu read and write ports 94 # 95 if ruby_port.support_data_reqs: 96 tester.cpuDataPort = ruby_port.slave 97 if ruby_port.support_inst_reqs: 98 tester.cpuInstPort = ruby_port.slave 99 100 # 101 # Tell the sequencer this is the ruby tester so that it 102 # copies the subblock back to the checker 103 # 104 ruby_port.using_ruby_tester = True 105 106 # 107 # Ruby doesn't need the backing image of memory when running with 108 # the tester. 109 # 110 ruby_port.access_phys_mem = False 111 112# ----------------------- 113# run simulation 114# ----------------------- 115 116root = Root(full_system = False, system = system ) 117root.system.mem_mode = 'timing' 118 119# Not much point in this being higher than the L1 latency 120m5.ticks.setGlobalFrequency('1ns') 121