rubytest-ruby.py revision 8933
18528SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 28528SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 38528SN/A# All rights reserved. 48825Snilay@cs.wisc.edu# 58528SN/A# Redistribution and use in source and binary forms, with or without 68528SN/A# modification, are permitted provided that the following conditions are 78528SN/A# met: redistributions of source code must retain the above copyright 88528SN/A# notice, this list of conditions and the following disclaimer; 98528SN/A# redistributions in binary form must reproduce the above copyright 108528SN/A# notice, this list of conditions and the following disclaimer in the 118891SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 128891SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 139536SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 148528SN/A# this software without specific prior written permission. 159348SAli.Saidi@ARM.com# 169265SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179055Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189348SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198528SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208528SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218528SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229536SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238528SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248528SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258528SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269449SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279481Snilay@cs.wisc.edu# 289079SAli.Saidi@ARM.com# Authors: Ron Dreslinski 298660SN/A# Brad Beckmann 308528SN/A 318528SN/Aimport m5 328528SN/Afrom m5.objects import * 338528SN/Afrom m5.defines import buildEnv 348528SN/Afrom m5.util import addToPath 358528SN/Aimport os, optparse, sys 368528SN/A 378528SN/A# Get paths we might need. It's expected this file is in m5/configs/example. 388528SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 398891SAli.Saidi@ARM.comconfig_root = os.path.dirname(config_path) 408528SN/Am5_root = os.path.dirname(config_root) 418528SN/AaddToPath(config_root+'/configs/common') 428528SN/AaddToPath(config_root+'/configs/ruby') 439348SAli.Saidi@ARM.com 448528SN/Aimport Ruby 458891SAli.Saidi@ARM.comimport Options 468721SN/A 478721SN/Aparser = optparse.OptionParser() 488891SAli.Saidi@ARM.comOptions.addCommonOptions(parser) 498891SAli.Saidi@ARM.com 508528SN/A# Add the ruby specific and protocol specific options 518528SN/ARuby.define_options(parser) 528528SN/A 538528SN/A(options, args) = parser.parse_args() 548528SN/A 558528SN/A# 568528SN/A# Set the default cache size and associativity to be very small to encourage 578528SN/A# races between requests and writebacks. 588528SN/A# 598528SN/Aoptions.l1d_size="256B" 608528SN/Aoptions.l1i_size="256B" 618528SN/Aoptions.l2_size="512B" 628528SN/Aoptions.l3_size="1kB" 638528SN/Aoptions.l1d_assoc=2 648528SN/Aoptions.l1i_assoc=2 658528SN/Aoptions.l2_assoc=2 668528SN/Aoptions.l3_assoc=2 678528SN/A 689536SAli.Saidi@ARM.com# Turn on flush check for the hammer protocol 698528SN/Acheck_flush = False 708528SN/Aif buildEnv['PROTOCOL'] == 'MOESI_hammer': 718528SN/A check_flush = True 728528SN/A 739481Snilay@cs.wisc.edu# 748528SN/A# create the tester and system, including ruby 758528SN/A# 768528SN/Atester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 778528SN/A wakeup_frequency = 10) 788528SN/A 798528SN/Asystem = System(tester = tester, physmem = SimpleMemory()) 808528SN/A 818528SN/ARuby.create_system(options, system) 829481Snilay@cs.wisc.edu 838528SN/Aassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 848528SN/A 858528SN/A# 868528SN/A# The tester is most effective when randomization is turned on and 878528SN/A# artifical delay is randomly inserted on messages 888528SN/A# 898528SN/Asystem.ruby.randomization = True 908528SN/A 918528SN/Afor ruby_port in system.ruby._cpu_ruby_ports: 928528SN/A # 938528SN/A # Tie the ruby tester ports to the ruby cpu ports 948528SN/A # 958528SN/A tester.cpuPort = ruby_port.slave 968528SN/A 978528SN/A # 988528SN/A # Tell the sequencer this is the ruby tester so that it 998528SN/A # copies the subblock back to the checker 1008528SN/A # 1018528SN/A ruby_port.using_ruby_tester = True 1028528SN/A 1038528SN/A # 1048528SN/A # Ruby doesn't need the backing image of memory when running with 1058528SN/A # the tester. 1068528SN/A # 1078528SN/A ruby_port.access_phys_mem = False 1088528SN/A 1098528SN/A# ----------------------- 1108528SN/A# run simulation 1118528SN/A# ----------------------- 1129449SAli.Saidi@ARM.com 1138528SN/Aroot = Root(full_system = False, system = system ) 1148528SN/Aroot.system.mem_mode = 'timing' 1158528SN/A 1168528SN/A# Not much point in this being higher than the L1 latency 1178528SN/Am5.ticks.setGlobalFrequency('1ns') 1188528SN/A