rubytest-ruby.py revision 11670
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36 37m5.util.addToPath('../configs/common') 38m5.util.addToPath('../configs/') 39 40from ruby import Ruby 41import Options 42 43parser = optparse.OptionParser() 44Options.addCommonOptions(parser) 45 46# Add the ruby specific and protocol specific options 47Ruby.define_options(parser) 48 49(options, args) = parser.parse_args() 50 51# 52# Set the default cache size and associativity to be very small to encourage 53# races between requests and writebacks. 54# 55options.l1d_size="256B" 56options.l1i_size="256B" 57options.l2_size="512B" 58options.l3_size="1kB" 59options.l1d_assoc=2 60options.l1i_assoc=2 61options.l2_assoc=2 62options.l3_assoc=2 63options.ports=32 64 65# Turn on flush check for the hammer protocol 66check_flush = False 67if buildEnv['PROTOCOL'] == 'MOESI_hammer': 68 check_flush = True 69 70# 71# create the tester and system, including ruby 72# 73tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 74 wakeup_frequency = 10, num_cpus = options.num_cpus) 75 76# We set the testers as cpu for ruby to find the correct clock domains 77# for the L1 Objects. 78system = System(cpu = tester) 79 80# Dummy voltage domain for all our clock domains 81system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 82system.clk_domain = SrcClockDomain(clock = '1GHz', 83 voltage_domain = system.voltage_domain) 84 85system.mem_ranges = AddrRange('256MB') 86 87Ruby.create_system(options, False, system) 88 89# Create a separate clock domain for Ruby 90system.ruby.clk_domain = SrcClockDomain(clock = '1GHz', 91 voltage_domain = system.voltage_domain) 92 93assert(options.num_cpus == len(system.ruby._cpu_ports)) 94 95tester.num_cpus = len(system.ruby._cpu_ports) 96 97# 98# The tester is most effective when randomization is turned on and 99# artifical delay is randomly inserted on messages 100# 101system.ruby.randomization = True 102 103for ruby_port in system.ruby._cpu_ports: 104 # 105 # Tie the ruby tester ports to the ruby cpu read and write ports 106 # 107 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: 108 tester.cpuInstDataPort = ruby_port.slave 109 elif ruby_port.support_data_reqs: 110 tester.cpuDataPort = ruby_port.slave 111 elif ruby_port.support_inst_reqs: 112 tester.cpuInstPort = ruby_port.slave 113 114 # Do not automatically retry stalled Ruby requests 115 ruby_port.no_retry_on_stall = True 116 117 # 118 # Tell the sequencer this is the ruby tester so that it 119 # copies the subblock back to the checker 120 # 121 ruby_port.using_ruby_tester = True 122 123# ----------------------- 124# run simulation 125# ----------------------- 126 127root = Root(full_system = False, system = system ) 128root.system.mem_mode = 'timing' 129 130# Not much point in this being higher than the L1 latency 131m5.ticks.setGlobalFrequency('1ns') 132