rubytest-ruby.py revision 11267
16928SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26928SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36928SBrad.Beckmann@amd.com# All rights reserved. 46928SBrad.Beckmann@amd.com# 56928SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66928SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76928SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86928SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96928SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106928SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116928SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126928SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136928SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146928SBrad.Beckmann@amd.com# this software without specific prior written permission. 156928SBrad.Beckmann@amd.com# 166928SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176928SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186928SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196928SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206928SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216928SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226928SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236928SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246928SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256928SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266928SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276928SBrad.Beckmann@amd.com# 286928SBrad.Beckmann@amd.com# Authors: Ron Dreslinski 296928SBrad.Beckmann@amd.com# Brad Beckmann 306928SBrad.Beckmann@amd.com 316928SBrad.Beckmann@amd.comimport m5 326928SBrad.Beckmann@amd.comfrom m5.objects import * 336928SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 346928SBrad.Beckmann@amd.comfrom m5.util import addToPath 356928SBrad.Beckmann@amd.comimport os, optparse, sys 366928SBrad.Beckmann@amd.com 376928SBrad.Beckmann@amd.com# Get paths we might need. It's expected this file is in m5/configs/example. 386928SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 396928SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 406928SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root) 416928SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/common') 426928SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/ruby') 439113SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/topologies') 446928SBrad.Beckmann@amd.com 456928SBrad.Beckmann@amd.comimport Ruby 468920Snilay@cs.wisc.eduimport Options 476928SBrad.Beckmann@amd.com 486928SBrad.Beckmann@amd.comparser = optparse.OptionParser() 498920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 506928SBrad.Beckmann@amd.com 517570SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 527570SBrad.Beckmann@amd.comRuby.define_options(parser) 536928SBrad.Beckmann@amd.com 546928SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 556928SBrad.Beckmann@amd.com 566928SBrad.Beckmann@amd.com# 577570SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 587570SBrad.Beckmann@amd.com# races between requests and writebacks. 597570SBrad.Beckmann@amd.com# 607570SBrad.Beckmann@amd.comoptions.l1d_size="256B" 617570SBrad.Beckmann@amd.comoptions.l1i_size="256B" 627570SBrad.Beckmann@amd.comoptions.l2_size="512B" 637570SBrad.Beckmann@amd.comoptions.l3_size="1kB" 647570SBrad.Beckmann@amd.comoptions.l1d_assoc=2 657570SBrad.Beckmann@amd.comoptions.l1i_assoc=2 667570SBrad.Beckmann@amd.comoptions.l2_assoc=2 677570SBrad.Beckmann@amd.comoptions.l3_assoc=2 689841Snilay@cs.wisc.eduoptions.ports=32 697570SBrad.Beckmann@amd.com 708933SBrad.Beckmann@amd.com# Turn on flush check for the hammer protocol 718933SBrad.Beckmann@amd.comcheck_flush = False 728933SBrad.Beckmann@amd.comif buildEnv['PROTOCOL'] == 'MOESI_hammer': 738933SBrad.Beckmann@amd.com check_flush = True 748933SBrad.Beckmann@amd.com 757570SBrad.Beckmann@amd.com# 766928SBrad.Beckmann@amd.com# create the tester and system, including ruby 776928SBrad.Beckmann@amd.com# 788933SBrad.Beckmann@amd.comtester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 798940SBrad.Beckmann@amd.com wakeup_frequency = 10, num_cpus = options.num_cpus) 806928SBrad.Beckmann@amd.com 8110300Scastilloe@unican.es# We set the testers as cpu for ruby to find the correct clock domains 8210300Scastilloe@unican.es# for the L1 Objects. 8310524Snilay@cs.wisc.edusystem = System(cpu = tester) 8410300Scastilloe@unican.es 859827Sakash.bagdia@arm.com# Dummy voltage domain for all our clock domains 869827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 879827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 889827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 896928SBrad.Beckmann@amd.com 909826Sandreas.hansson@arm.comsystem.mem_ranges = AddrRange('256MB') 919826Sandreas.hansson@arm.com 9210519Snilay@cs.wisc.eduRuby.create_system(options, False, system) 936928SBrad.Beckmann@amd.com 949793Sakash.bagdia@arm.com# Create a separate clock domain for Ruby 959827Sakash.bagdia@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = '1GHz', 969827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 979793Sakash.bagdia@arm.com 9810120Snilay@cs.wisc.eduassert(options.num_cpus == len(system.ruby._cpu_ports)) 996928SBrad.Beckmann@amd.com 10011267SBrad.Beckmann@amd.comtester.num_cpus = len(system.ruby._cpu_ports) 10111267SBrad.Beckmann@amd.com 1026928SBrad.Beckmann@amd.com# 1036928SBrad.Beckmann@amd.com# The tester is most effective when randomization is turned on and 1046928SBrad.Beckmann@amd.com# artifical delay is randomly inserted on messages 1056928SBrad.Beckmann@amd.com# 1066928SBrad.Beckmann@amd.comsystem.ruby.randomization = True 1076928SBrad.Beckmann@amd.com 10810120Snilay@cs.wisc.edufor ruby_port in system.ruby._cpu_ports: 1096928SBrad.Beckmann@amd.com # 1108940SBrad.Beckmann@amd.com # Tie the ruby tester ports to the ruby cpu read and write ports 1116928SBrad.Beckmann@amd.com # 11211267SBrad.Beckmann@amd.com if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: 11311267SBrad.Beckmann@amd.com tester.cpuInstDataPort = ruby_port.slave 11411267SBrad.Beckmann@amd.com elif ruby_port.support_data_reqs: 11511267SBrad.Beckmann@amd.com tester.cpuDataPort = ruby_port.slave 11611267SBrad.Beckmann@amd.com elif ruby_port.support_inst_reqs: 11711267SBrad.Beckmann@amd.com tester.cpuInstPort = ruby_port.slave 11811267SBrad.Beckmann@amd.com 11911267SBrad.Beckmann@amd.com # Do not automatically retry stalled Ruby requests 12011267SBrad.Beckmann@amd.com ruby_port.no_retry_on_stall = True 1216928SBrad.Beckmann@amd.com 1226928SBrad.Beckmann@amd.com # 1236928SBrad.Beckmann@amd.com # Tell the sequencer this is the ruby tester so that it 1246928SBrad.Beckmann@amd.com # copies the subblock back to the checker 1256928SBrad.Beckmann@amd.com # 1266928SBrad.Beckmann@amd.com ruby_port.using_ruby_tester = True 1276928SBrad.Beckmann@amd.com 1286928SBrad.Beckmann@amd.com# ----------------------- 1296928SBrad.Beckmann@amd.com# run simulation 1306928SBrad.Beckmann@amd.com# ----------------------- 1316928SBrad.Beckmann@amd.com 1328801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system ) 1336928SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing' 1346928SBrad.Beckmann@amd.com 1356928SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency 1366928SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns') 137