realview-simple-timing.py revision 9310:aa7bf10e822a 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Caches import *
34
35#cpu
36cpu = TimingSimpleCPU(cpu_id=0)
37#the system
38system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
39
40system.cpu = cpu
41
42#create the iocache
43system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
44system.iocache.cpu_side = system.iobus.master
45system.iocache.mem_side = system.membus.slave
46
47#connect up the cpu and caches
48cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
49                              L1(size = '32kB', assoc = 4),
50                              L2(size = '4MB', assoc = 8))
51# create the interrupt controller
52cpu.createInterruptController()
53# connect cpu and caches to the rest of the system
54cpu.connectAllPorts(system.membus)
55# set the cpu clock along with the caches and l1-l2 bus
56cpu.clock = '2GHz'
57
58root = Root(full_system=True, system=system)
59m5.ticks.setGlobalFrequency('1THz')
60
61