realview-simple-atomic.py revision 9282
17735SAli.Saidi@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27735SAli.Saidi@ARM.com# All rights reserved. 37735SAli.Saidi@ARM.com# 47735SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 57735SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 67735SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 77735SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 87735SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 97735SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 107735SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 117735SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 127735SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 137735SAli.Saidi@ARM.com# this software without specific prior written permission. 147735SAli.Saidi@ARM.com# 157735SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167735SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177735SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187735SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197735SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207735SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217735SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227735SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237735SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247735SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257735SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267735SAli.Saidi@ARM.com# 277735SAli.Saidi@ARM.com# Authors: Steve Reinhardt 287735SAli.Saidi@ARM.com 297735SAli.Saidi@ARM.comimport m5 307735SAli.Saidi@ARM.comfrom m5.objects import * 317735SAli.Saidi@ARM.comm5.util.addToPath('../configs/common') 327735SAli.Saidi@ARM.comimport FSConfig 337735SAli.Saidi@ARM.com 347735SAli.Saidi@ARM.com# -------------------- 357735SAli.Saidi@ARM.com# Base L1 Cache 367735SAli.Saidi@ARM.com# ==================== 377735SAli.Saidi@ARM.com 387735SAli.Saidi@ARM.comclass L1(BaseCache): 399263Smrinmoy.ghosh@arm.com hit_latency = '1ns' 409263Smrinmoy.ghosh@arm.com response_latency = '1ns' 417735SAli.Saidi@ARM.com block_size = 64 427735SAli.Saidi@ARM.com mshrs = 4 437735SAli.Saidi@ARM.com tgts_per_mshr = 8 448134SAli.Saidi@ARM.com is_top_level = True 457735SAli.Saidi@ARM.com 467735SAli.Saidi@ARM.com# ---------------------- 477735SAli.Saidi@ARM.com# Base L2 Cache 487735SAli.Saidi@ARM.com# ---------------------- 497735SAli.Saidi@ARM.com 507735SAli.Saidi@ARM.comclass L2(BaseCache): 517735SAli.Saidi@ARM.com block_size = 64 529263Smrinmoy.ghosh@arm.com hit_latency = '10ns' 539263Smrinmoy.ghosh@arm.com response_latency = '10ns' 547735SAli.Saidi@ARM.com mshrs = 92 557735SAli.Saidi@ARM.com tgts_per_mshr = 16 567735SAli.Saidi@ARM.com write_buffers = 8 577735SAli.Saidi@ARM.com 587735SAli.Saidi@ARM.com# --------------------- 597735SAli.Saidi@ARM.com# I/O Cache 607735SAli.Saidi@ARM.com# --------------------- 617735SAli.Saidi@ARM.comclass IOCache(BaseCache): 627735SAli.Saidi@ARM.com assoc = 8 637735SAli.Saidi@ARM.com block_size = 64 649263Smrinmoy.ghosh@arm.com hit_latency = '50ns' 659263Smrinmoy.ghosh@arm.com response_latency = '50ns' 667735SAli.Saidi@ARM.com mshrs = 20 677735SAli.Saidi@ARM.com size = '1kB' 687735SAli.Saidi@ARM.com tgts_per_mshr = 12 698883SAli.Saidi@ARM.com addr_ranges = [AddrRange(0, size='256MB')] 707735SAli.Saidi@ARM.com forward_snoops = False 717735SAli.Saidi@ARM.com 727735SAli.Saidi@ARM.com#cpu 737735SAli.Saidi@ARM.comcpu = AtomicSimpleCPU(cpu_id=0) 747735SAli.Saidi@ARM.com#the system 758061SAli.Saidi@ARM.comsystem = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 769282Sandreas.hansson@arm.com 779282Sandreas.hansson@arm.comsystem.cpu = cpu 789282Sandreas.hansson@arm.com 799282Sandreas.hansson@arm.com#create the iocache 807735SAli.Saidi@ARM.comsystem.iocache = IOCache() 818839Sandreas.hansson@arm.comsystem.iocache.cpu_side = system.iobus.master 828839Sandreas.hansson@arm.comsystem.iocache.mem_side = system.membus.slave 837735SAli.Saidi@ARM.com 849282Sandreas.hansson@arm.com#connect up the cpu and caches 859282Sandreas.hansson@arm.comcpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 869282Sandreas.hansson@arm.com L1(size = '32kB', assoc = 4), 879282Sandreas.hansson@arm.com L2(size = '4MB', assoc = 8)) 888876Sandreas.hansson@arm.com# create the interrupt controller 898876Sandreas.hansson@arm.comcpu.createInterruptController() 909282Sandreas.hansson@arm.com# connect cpu and caches to the rest of the system 919282Sandreas.hansson@arm.comcpu.connectAllPorts(system.membus) 929282Sandreas.hansson@arm.com# set the cpu clock along with the caches and l1-l2 bus 937735SAli.Saidi@ARM.comcpu.clock = '2GHz' 947735SAli.Saidi@ARM.com 958801Sgblack@eecs.umich.eduroot = Root(full_system=True, system=system) 967735SAli.Saidi@ARM.comm5.ticks.setGlobalFrequency('1THz') 977735SAli.Saidi@ARM.com 98