realview-o3.py revision 8150
18150SAli.Saidi@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 28150SAli.Saidi@ARM.com# All rights reserved. 38150SAli.Saidi@ARM.com# 48150SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 58150SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 68150SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 78150SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 88150SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 98150SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 108150SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 118150SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 128150SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 138150SAli.Saidi@ARM.com# this software without specific prior written permission. 148150SAli.Saidi@ARM.com# 158150SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168150SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178150SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188150SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198150SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208150SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218150SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228150SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238150SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248150SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258150SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268150SAli.Saidi@ARM.com# 278150SAli.Saidi@ARM.com# Authors: Steve Reinhardt 288150SAli.Saidi@ARM.com 298150SAli.Saidi@ARM.comimport m5 308150SAli.Saidi@ARM.comfrom m5.objects import * 318150SAli.Saidi@ARM.comm5.util.addToPath('../configs/common') 328150SAli.Saidi@ARM.comimport FSConfig 338150SAli.Saidi@ARM.com 348150SAli.Saidi@ARM.com 358150SAli.Saidi@ARM.com# -------------------- 368150SAli.Saidi@ARM.com# Base L1 Cache 378150SAli.Saidi@ARM.com# ==================== 388150SAli.Saidi@ARM.com 398150SAli.Saidi@ARM.comclass L1(BaseCache): 408150SAli.Saidi@ARM.com latency = '1ns' 418150SAli.Saidi@ARM.com block_size = 64 428150SAli.Saidi@ARM.com mshrs = 4 438150SAli.Saidi@ARM.com tgts_per_mshr = 8 448150SAli.Saidi@ARM.com is_top_level = True 458150SAli.Saidi@ARM.com 468150SAli.Saidi@ARM.com# ---------------------- 478150SAli.Saidi@ARM.com# Base L2 Cache 488150SAli.Saidi@ARM.com# ---------------------- 498150SAli.Saidi@ARM.com 508150SAli.Saidi@ARM.comclass L2(BaseCache): 518150SAli.Saidi@ARM.com block_size = 64 528150SAli.Saidi@ARM.com latency = '10ns' 538150SAli.Saidi@ARM.com mshrs = 92 548150SAli.Saidi@ARM.com tgts_per_mshr = 16 558150SAli.Saidi@ARM.com write_buffers = 8 568150SAli.Saidi@ARM.com 578150SAli.Saidi@ARM.com# --------------------- 588150SAli.Saidi@ARM.com# I/O Cache 598150SAli.Saidi@ARM.com# --------------------- 608150SAli.Saidi@ARM.comclass IOCache(BaseCache): 618150SAli.Saidi@ARM.com assoc = 8 628150SAli.Saidi@ARM.com block_size = 64 638150SAli.Saidi@ARM.com latency = '50ns' 648150SAli.Saidi@ARM.com mshrs = 20 658150SAli.Saidi@ARM.com size = '1kB' 668150SAli.Saidi@ARM.com tgts_per_mshr = 12 678150SAli.Saidi@ARM.com addr_range=AddrRange(0, size='128MB') 688150SAli.Saidi@ARM.com forward_snoops = False 698150SAli.Saidi@ARM.com 708150SAli.Saidi@ARM.com#cpu 718150SAli.Saidi@ARM.comcpu = DerivO3CPU(cpu_id=0) 728150SAli.Saidi@ARM.com#the system 738150SAli.Saidi@ARM.comsystem = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 748150SAli.Saidi@ARM.com 758150SAli.Saidi@ARM.comsystem.cpu = cpu 768150SAli.Saidi@ARM.com#create the l1/l2 bus 778150SAli.Saidi@ARM.comsystem.toL2Bus = Bus() 788150SAli.Saidi@ARM.comsystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 798150SAli.Saidi@ARM.comsystem.bridge.filter_ranges_b=[AddrRange(0, size='128MB')] 808150SAli.Saidi@ARM.comsystem.iocache = IOCache() 818150SAli.Saidi@ARM.comsystem.iocache.cpu_side = system.iobus.port 828150SAli.Saidi@ARM.comsystem.iocache.mem_side = system.membus.port 838150SAli.Saidi@ARM.com 848150SAli.Saidi@ARM.com 858150SAli.Saidi@ARM.com#connect up the l2 cache 868150SAli.Saidi@ARM.comsystem.l2c = L2(size='4MB', assoc=8) 878150SAli.Saidi@ARM.comsystem.l2c.cpu_side = system.toL2Bus.port 888150SAli.Saidi@ARM.comsystem.l2c.mem_side = system.membus.port 898150SAli.Saidi@ARM.com 908150SAli.Saidi@ARM.com#connect up the cpu and l1s 918150SAli.Saidi@ARM.comcpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 928150SAli.Saidi@ARM.com L1(size = '32kB', assoc = 4)) 938150SAli.Saidi@ARM.com# connect cpu level-1 caches to shared level-2 cache 948150SAli.Saidi@ARM.comcpu.connectAllPorts(system.toL2Bus, system.membus) 958150SAli.Saidi@ARM.comcpu.clock = '2GHz' 968150SAli.Saidi@ARM.com 978150SAli.Saidi@ARM.comroot = Root(system=system) 988150SAli.Saidi@ARM.comm5.ticks.setGlobalFrequency('1THz') 998150SAli.Saidi@ARM.com 100