realview-o3-dual.py revision 9315:2e00867b5001 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Benchmarks import *
34from Caches import *
35
36#cpu
37cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
38#the system
39system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
40system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
41system.iocache.cpu_side = system.iobus.master
42system.iocache.mem_side = system.membus.slave
43
44system.cpu = cpus
45#create the l1/l2 bus
46system.toL2Bus = CoherentBus(clock = '2GHz')
47
48#connect up the l2 cache
49system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
50system.l2c.cpu_side = system.toL2Bus.master
51system.l2c.mem_side = system.membus.slave
52
53#connect up the cpu and l1s
54for c in cpus:
55    c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
56                              L1Cache(size = '32kB', assoc = 4))
57    # create the interrupt controller
58    c.createInterruptController()
59    # connect cpu level-1 caches to shared level-2 cache
60    c.connectAllPorts(system.toL2Bus, system.membus)
61    c.clock = '2GHz'
62
63
64root = Root(full_system=True, system=system)
65m5.ticks.setGlobalFrequency('1THz')
66
67