realview-o3-dual.py revision 9263:066099902102 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Benchmarks import *
34
35# --------------------
36# Base L1 Cache
37# ====================
38
39class L1(BaseCache):
40    hit_latency = '1ns'
41    response_latency = '1ns'
42    block_size = 64
43    mshrs = 4
44    tgts_per_mshr = 20
45    is_top_level = True
46
47# ----------------------
48# Base L2 Cache
49# ----------------------
50
51class L2(BaseCache):
52    block_size = 64
53    hit_latency = '10ns'
54    response_latency = '10ns'
55    mshrs = 92
56    tgts_per_mshr = 16
57    write_buffers = 8
58
59# ---------------------
60# I/O Cache
61# ---------------------
62class IOCache(BaseCache):
63    assoc = 8
64    block_size = 64
65    hit_latency = '50ns'
66    response_latency = '50ns'
67    mshrs = 20
68    size = '1kB'
69    tgts_per_mshr = 12
70    addr_ranges = [AddrRange(0, size='256MB')]
71    forward_snoops = False
72
73#cpu
74cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
75#the system
76system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
77system.iocache = IOCache()
78system.iocache.cpu_side = system.iobus.master
79system.iocache.mem_side = system.membus.slave
80
81system.cpu = cpus
82#create the l1/l2 bus
83system.toL2Bus = CoherentBus()
84
85#connect up the l2 cache
86system.l2c = L2(size='4MB', assoc=8)
87system.l2c.cpu_side = system.toL2Bus.master
88system.l2c.mem_side = system.membus.slave
89
90#connect up the cpu and l1s
91for c in cpus:
92    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
93                                L1(size = '32kB', assoc = 4))
94    # create the interrupt controller
95    c.createInterruptController()
96    # connect cpu level-1 caches to shared level-2 cache
97    c.connectAllPorts(system.toL2Bus, system.membus)
98    c.clock = '2GHz'
99
100
101root = Root(full_system=True, system=system)
102m5.ticks.setGlobalFrequency('1THz')
103
104