realview-o3-dual.py revision 8528
18528SAli.Saidi@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 28528SAli.Saidi@ARM.com# All rights reserved. 38528SAli.Saidi@ARM.com# 48528SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 58528SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 68528SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 78528SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 88528SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 98528SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 108528SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 118528SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 128528SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 138528SAli.Saidi@ARM.com# this software without specific prior written permission. 148528SAli.Saidi@ARM.com# 158528SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168528SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178528SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188528SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198528SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208528SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218528SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228528SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238528SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248528SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258528SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268528SAli.Saidi@ARM.com# 278528SAli.Saidi@ARM.com# Authors: Steve Reinhardt 288528SAli.Saidi@ARM.com 298528SAli.Saidi@ARM.comimport m5 308528SAli.Saidi@ARM.comfrom m5.objects import * 318528SAli.Saidi@ARM.comm5.util.addToPath('../configs/common') 328528SAli.Saidi@ARM.comimport FSConfig 338528SAli.Saidi@ARM.comfrom Benchmarks import * 348528SAli.Saidi@ARM.com 358528SAli.Saidi@ARM.com# -------------------- 368528SAli.Saidi@ARM.com# Base L1 Cache 378528SAli.Saidi@ARM.com# ==================== 388528SAli.Saidi@ARM.com 398528SAli.Saidi@ARM.comclass L1(BaseCache): 408528SAli.Saidi@ARM.com latency = '1ns' 418528SAli.Saidi@ARM.com block_size = 64 428528SAli.Saidi@ARM.com mshrs = 4 438528SAli.Saidi@ARM.com tgts_per_mshr = 8 448528SAli.Saidi@ARM.com is_top_level = True 458528SAli.Saidi@ARM.com 468528SAli.Saidi@ARM.com# ---------------------- 478528SAli.Saidi@ARM.com# Base L2 Cache 488528SAli.Saidi@ARM.com# ---------------------- 498528SAli.Saidi@ARM.com 508528SAli.Saidi@ARM.comclass L2(BaseCache): 518528SAli.Saidi@ARM.com block_size = 64 528528SAli.Saidi@ARM.com latency = '10ns' 538528SAli.Saidi@ARM.com mshrs = 92 548528SAli.Saidi@ARM.com tgts_per_mshr = 16 558528SAli.Saidi@ARM.com write_buffers = 8 568528SAli.Saidi@ARM.com 578528SAli.Saidi@ARM.com# --------------------- 588528SAli.Saidi@ARM.com# I/O Cache 598528SAli.Saidi@ARM.com# --------------------- 608528SAli.Saidi@ARM.comclass IOCache(BaseCache): 618528SAli.Saidi@ARM.com assoc = 8 628528SAli.Saidi@ARM.com block_size = 64 638528SAli.Saidi@ARM.com latency = '50ns' 648528SAli.Saidi@ARM.com mshrs = 20 658528SAli.Saidi@ARM.com size = '1kB' 668528SAli.Saidi@ARM.com tgts_per_mshr = 12 678528SAli.Saidi@ARM.com addr_range=AddrRange(0, size='256MB') 688528SAli.Saidi@ARM.com forward_snoops = False 698528SAli.Saidi@ARM.com 708528SAli.Saidi@ARM.com#cpu 718528SAli.Saidi@ARM.comcpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ] 728528SAli.Saidi@ARM.com#the system 738528SAli.Saidi@ARM.comsystem = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 748528SAli.Saidi@ARM.comsystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 758528SAli.Saidi@ARM.comsystem.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] 768528SAli.Saidi@ARM.comsystem.iocache = IOCache() 778528SAli.Saidi@ARM.comsystem.iocache.cpu_side = system.iobus.port 788528SAli.Saidi@ARM.comsystem.iocache.mem_side = system.membus.port 798528SAli.Saidi@ARM.com 808528SAli.Saidi@ARM.comsystem.cpu = cpus 818528SAli.Saidi@ARM.com#create the l1/l2 bus 828528SAli.Saidi@ARM.comsystem.toL2Bus = Bus() 838528SAli.Saidi@ARM.com 848528SAli.Saidi@ARM.com#connect up the l2 cache 858528SAli.Saidi@ARM.comsystem.l2c = L2(size='4MB', assoc=8) 868528SAli.Saidi@ARM.comsystem.l2c.cpu_side = system.toL2Bus.port 878528SAli.Saidi@ARM.comsystem.l2c.mem_side = system.membus.port 888528SAli.Saidi@ARM.comsystem.l2c.num_cpus = 2 898528SAli.Saidi@ARM.com 908528SAli.Saidi@ARM.com#connect up the cpu and l1s 918528SAli.Saidi@ARM.comfor c in cpus: 928528SAli.Saidi@ARM.com c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 938528SAli.Saidi@ARM.com L1(size = '32kB', assoc = 4)) 948528SAli.Saidi@ARM.com # connect cpu level-1 caches to shared level-2 cache 958528SAli.Saidi@ARM.com c.connectAllPorts(system.toL2Bus, system.membus) 968528SAli.Saidi@ARM.com c.clock = '2GHz' 978528SAli.Saidi@ARM.com 988528SAli.Saidi@ARM.com 998528SAli.Saidi@ARM.comroot = Root(system=system) 1008528SAli.Saidi@ARM.comm5.ticks.setGlobalFrequency('1THz') 1018528SAli.Saidi@ARM.com 102