realview-o3-checker.py revision 9282:ac627fdc8991 
1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
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8# licensed hereunder.  You may use the software subject to the license
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15# met: redistributions of source code must retain the above copyright
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17# redistributions in binary form must reproduce the above copyright
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22# this software without specific prior written permission.
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24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35#
36# Authors: Geoffrey Blake
37
38import m5
39from m5.objects import *
40m5.util.addToPath('../configs/common')
41import FSConfig
42
43
44# --------------------
45# Base L1 Cache
46# ====================
47
48class L1(BaseCache):
49    hit_latency = '1ns'
50    response_latency = '1ns'
51    block_size = 64
52    mshrs = 4
53    tgts_per_mshr = 20
54    is_top_level = True
55
56# ----------------------
57# Base L2 Cache
58# ----------------------
59
60class L2(BaseCache):
61    block_size = 64
62    hit_latency = '10ns'
63    response_latency = '10ns'
64    mshrs = 92
65    tgts_per_mshr = 16
66    write_buffers = 8
67
68# ---------------------
69# I/O Cache
70# ---------------------
71class IOCache(BaseCache):
72    assoc = 8
73    block_size = 64
74    hit_latency = '50ns'
75    response_latency = '50ns'
76    mshrs = 20
77    size = '1kB'
78    tgts_per_mshr = 12
79    addr_ranges = [AddrRange(0, size='256MB')]
80    forward_snoops = False
81
82#cpu
83cpu = DerivO3CPU(cpu_id=0)
84#the system
85system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
86
87system.cpu = cpu
88#connect up the checker
89cpu.addCheckerCpu()
90
91#create the iocache
92system.iocache = IOCache()
93system.iocache.cpu_side = system.iobus.master
94system.iocache.mem_side = system.membus.slave
95
96#connect up the cpu and caches
97cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
98                              L1(size = '32kB', assoc = 4),
99                              L2(size = '4MB', assoc = 8))
100# create the interrupt controller
101cpu.createInterruptController()
102# connect cpu and caches to the rest of the system
103cpu.connectAllPorts(system.membus)
104# set the cpu clock along with the caches and l1-l2 bus
105cpu.clock = '2GHz'
106
107root = Root(full_system=True, system=system)
108m5.ticks.setGlobalFrequency('1THz')
109
110