realview-o3-checker.py revision 8889:2e38fd9937a9 
1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
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14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
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20# neither the name of the copyright holders nor the names of its
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22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35#
36# Authors: Geoffrey Blake
37
38import m5
39from m5.objects import *
40m5.util.addToPath('../configs/common')
41import FSConfig
42
43
44# --------------------
45# Base L1 Cache
46# ====================
47
48class L1(BaseCache):
49    latency = '1ns'
50    block_size = 64
51    mshrs = 4
52    tgts_per_mshr = 20
53    is_top_level = True
54
55# ----------------------
56# Base L2 Cache
57# ----------------------
58
59class L2(BaseCache):
60    block_size = 64
61    latency = '10ns'
62    mshrs = 92
63    tgts_per_mshr = 16
64    write_buffers = 8
65
66# ---------------------
67# I/O Cache
68# ---------------------
69class IOCache(BaseCache):
70    assoc = 8
71    block_size = 64
72    latency = '50ns'
73    mshrs = 20
74    size = '1kB'
75    tgts_per_mshr = 12
76    addr_ranges = [AddrRange(0, size='256MB')]
77    forward_snoops = False
78
79#cpu
80cpu = DerivO3CPU(cpu_id=0)
81#the system
82system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
83
84system.cpu = cpu
85#create the l1/l2 bus
86system.toL2Bus = Bus()
87system.iocache = IOCache()
88system.iocache.cpu_side = system.iobus.master
89system.iocache.mem_side = system.membus.slave
90
91
92#connect up the l2 cache
93system.l2c = L2(size='4MB', assoc=8)
94system.l2c.cpu_side = system.toL2Bus.master
95system.l2c.mem_side = system.membus.slave
96
97#connect up the checker
98cpu.addCheckerCpu()
99#connect up the cpu and l1s
100cpu.createInterruptController()
101cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
102                            L1(size = '32kB', assoc = 4))
103# connect cpu level-1 caches to shared level-2 cache
104cpu.connectAllPorts(system.toL2Bus, system.membus)
105cpu.clock = '2GHz'
106
107root = Root(full_system=True, system=system)
108m5.ticks.setGlobalFrequency('1THz')
109
110