pc-simple-timing.py revision 7926
17926Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 27926Sgblack@eecs.umich.edu# All rights reserved. 37926Sgblack@eecs.umich.edu# 47926Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 57926Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 67926Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 77926Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 87926Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 97926Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 107926Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 117926Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 127926Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 137926Sgblack@eecs.umich.edu# this software without specific prior written permission. 147926Sgblack@eecs.umich.edu# 157926Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167926Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177926Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187926Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197926Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207926Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217926Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227926Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237926Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247926Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257926Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267926Sgblack@eecs.umich.edu# 277926Sgblack@eecs.umich.edu# Authors: Steve Reinhardt 287926Sgblack@eecs.umich.edu 297926Sgblack@eecs.umich.eduimport m5 307926Sgblack@eecs.umich.edufrom m5.objects import * 317926Sgblack@eecs.umich.edum5.util.addToPath('../configs/common') 327926Sgblack@eecs.umich.edufrom Benchmarks import SysConfig 337926Sgblack@eecs.umich.eduimport FSConfig 347926Sgblack@eecs.umich.edu 357926Sgblack@eecs.umich.edu 367926Sgblack@eecs.umich.edumem_size = '128MB' 377926Sgblack@eecs.umich.edu 387926Sgblack@eecs.umich.edu# -------------------- 397926Sgblack@eecs.umich.edu# Base L1 Cache 407926Sgblack@eecs.umich.edu# ==================== 417926Sgblack@eecs.umich.edu 427926Sgblack@eecs.umich.educlass L1(BaseCache): 437926Sgblack@eecs.umich.edu latency = '1ns' 447926Sgblack@eecs.umich.edu block_size = 64 457926Sgblack@eecs.umich.edu mshrs = 4 467926Sgblack@eecs.umich.edu tgts_per_mshr = 8 477926Sgblack@eecs.umich.edu 487926Sgblack@eecs.umich.edu# ---------------------- 497926Sgblack@eecs.umich.edu# Base L2 Cache 507926Sgblack@eecs.umich.edu# ---------------------- 517926Sgblack@eecs.umich.edu 527926Sgblack@eecs.umich.educlass L2(BaseCache): 537926Sgblack@eecs.umich.edu block_size = 64 547926Sgblack@eecs.umich.edu latency = '10ns' 557926Sgblack@eecs.umich.edu mshrs = 92 567926Sgblack@eecs.umich.edu tgts_per_mshr = 16 577926Sgblack@eecs.umich.edu write_buffers = 8 587926Sgblack@eecs.umich.edu 597926Sgblack@eecs.umich.edu# --------------------- 607926Sgblack@eecs.umich.edu# Page table walker cache 617926Sgblack@eecs.umich.edu# --------------------- 627926Sgblack@eecs.umich.educlass PageTableWalkerCache(BaseCache): 637926Sgblack@eecs.umich.edu assoc = 2 647926Sgblack@eecs.umich.edu block_size = 64 657926Sgblack@eecs.umich.edu latency = '1ns' 667926Sgblack@eecs.umich.edu mshrs = 10 677926Sgblack@eecs.umich.edu size = '1kB' 687926Sgblack@eecs.umich.edu tgts_per_mshr = 12 697926Sgblack@eecs.umich.edu 707926Sgblack@eecs.umich.edu# --------------------- 717926Sgblack@eecs.umich.edu# I/O Cache 727926Sgblack@eecs.umich.edu# --------------------- 737926Sgblack@eecs.umich.educlass IOCache(BaseCache): 747926Sgblack@eecs.umich.edu assoc = 8 757926Sgblack@eecs.umich.edu block_size = 64 767926Sgblack@eecs.umich.edu latency = '50ns' 777926Sgblack@eecs.umich.edu mshrs = 20 787926Sgblack@eecs.umich.edu size = '1kB' 797926Sgblack@eecs.umich.edu tgts_per_mshr = 12 807926Sgblack@eecs.umich.edu addr_range = AddrRange(0, size=mem_size) 817926Sgblack@eecs.umich.edu forward_snoops = False 827926Sgblack@eecs.umich.edu 837926Sgblack@eecs.umich.edu#cpu 847926Sgblack@eecs.umich.educpu = TimingSimpleCPU(cpu_id=0) 857926Sgblack@eecs.umich.edu#the system 867926Sgblack@eecs.umich.edumdesc = SysConfig(disk = 'linux-x86.img') 877926Sgblack@eecs.umich.edusystem = FSConfig.makeLinuxX86System('timing', mdesc = mdesc) 887926Sgblack@eecs.umich.edusystem.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 897926Sgblack@eecs.umich.edu 907926Sgblack@eecs.umich.edusystem.cpu = cpu 917926Sgblack@eecs.umich.edu#create the l1/l2 bus 927926Sgblack@eecs.umich.edusystem.toL2Bus = Bus() 937926Sgblack@eecs.umich.edusystem.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)] 947926Sgblack@eecs.umich.edusystem.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)] 957926Sgblack@eecs.umich.edusystem.iocache = IOCache(addr_range=mem_size) 967926Sgblack@eecs.umich.edusystem.iocache.cpu_side = system.iobus.port 977926Sgblack@eecs.umich.edusystem.iocache.mem_side = system.membus.port 987926Sgblack@eecs.umich.edu 997926Sgblack@eecs.umich.edu 1007926Sgblack@eecs.umich.edu#connect up the l2 cache 1017926Sgblack@eecs.umich.edusystem.l2c = L2(size='4MB', assoc=8) 1027926Sgblack@eecs.umich.edusystem.l2c.cpu_side = system.toL2Bus.port 1037926Sgblack@eecs.umich.edusystem.l2c.mem_side = system.membus.port 1047926Sgblack@eecs.umich.edu 1057926Sgblack@eecs.umich.edu#connect up the cpu and l1s 1067926Sgblack@eecs.umich.educpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 1077926Sgblack@eecs.umich.edu L1(size = '32kB', assoc = 4), 1087926Sgblack@eecs.umich.edu PageTableWalkerCache(), 1097926Sgblack@eecs.umich.edu PageTableWalkerCache()) 1107926Sgblack@eecs.umich.edu# connect cpu level-1 caches to shared level-2 cache 1117926Sgblack@eecs.umich.educpu.connectAllPorts(system.toL2Bus, system.membus) 1127926Sgblack@eecs.umich.educpu.clock = '2GHz' 1137926Sgblack@eecs.umich.edu 1147926Sgblack@eecs.umich.eduroot = Root(system=system) 1157926Sgblack@eecs.umich.edum5.ticks.setGlobalFrequency('1THz') 1167926Sgblack@eecs.umich.edu 117