pc-simple-timing-ruby.py revision 9665:6dbdeee787cc 
1# Copyright (c) 2012 Mark D. Hill and David A. Wood
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nilay Vaish
28
29import m5, os, optparse, sys
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34
35m5.util.addToPath('../configs/ruby')
36m5.util.addToPath('../configs/topologies')
37import Ruby
38import Options
39
40# Add the ruby specific and protocol specific options
41parser = optparse.OptionParser()
42Options.addCommonOptions(parser)
43Ruby.define_options(parser)
44(options, args) = parser.parse_args()
45
46# Set the default cache size and associativity to be very small to encourage
47# races between requests and writebacks.
48options.l1d_size="32kB"
49options.l1i_size="32kB"
50options.l2_size="4MB"
51options.l1d_assoc=2
52options.l1i_assoc=2
53options.l2_assoc=2
54options.num_cpus = 2
55
56#the system
57mdesc = SysConfig(disk = 'linux-x86.img')
58system = FSConfig.makeLinuxX86System('timing', SimpleDDR3, options.num_cpus,
59                                     mdesc=mdesc, Ruby=True)
60system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
61system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
62Ruby.create_system(options, system, system.piobus, system._dma_ports)
63
64for (i, cpu) in enumerate(system.cpu):
65    # create the interrupt controller
66    cpu.createInterruptController()
67    # Tie the cpu ports to the correct ruby system ports
68    cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
69    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
70    cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
71    cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
72    cpu.interrupts.pio = system.piobus.master
73    cpu.interrupts.int_master = system.piobus.slave
74    cpu.interrupts.int_slave = system.piobus.master
75    cpu.clock = '2GHz'
76
77    # Set access_phys_mem to True for ruby port
78    system.ruby._cpu_ruby_ports[i].access_phys_mem = True
79
80root = Root(full_system = True, system = system)
81m5.ticks.setGlobalFrequency('1THz')
82