pc-simple-atomic.py revision 9310:aa7bf10e822a 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34from Caches import *
35
36mem_size = '128MB'
37
38#cpu
39cpu = AtomicSimpleCPU(cpu_id=0)
40#the system
41mdesc = SysConfig(disk = 'linux-x86.img')
42system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
43system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
44
45system.cpu = cpu
46
47#create the iocache
48system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
49system.iocache.cpu_side = system.iobus.master
50system.iocache.mem_side = system.membus.slave
51
52#connect up the cpu and caches
53cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
54                              L1(size = '32kB', assoc = 4),
55                              L2(size = '4MB', assoc = 8),
56                              PageTableWalkerCache(),
57                              PageTableWalkerCache())
58# create the interrupt controller
59cpu.createInterruptController()
60# connect cpu and caches to the rest of the system
61cpu.connectAllPorts(system.membus)
62# set the cpu clock along with the caches and l1-l2 bus
63cpu.clock = '2GHz'
64
65root = Root(full_system=True, system=system)
66m5.ticks.setGlobalFrequency('1THz')
67
68