pc-simple-atomic.py revision 9036:6385cf85bf12 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34
35mem_size = '128MB'
36
37# --------------------
38# Base L1 Cache
39# ====================
40
41class L1(BaseCache):
42    latency = '1ns'
43    block_size = 64
44    mshrs = 4
45    tgts_per_mshr = 8
46    is_top_level = True
47
48# ----------------------
49# Base L2 Cache
50# ----------------------
51
52class L2(BaseCache):
53    block_size = 64
54    latency = '10ns'
55    mshrs = 92
56    tgts_per_mshr = 16
57    write_buffers = 8
58
59# ---------------------
60# Page table walker cache
61# ---------------------
62class PageTableWalkerCache(BaseCache):
63    assoc = 2
64    block_size = 64
65    latency = '1ns'
66    mshrs = 10
67    size = '1kB'
68    tgts_per_mshr = 12
69    is_top_level = True
70
71# ---------------------
72# I/O Cache
73# ---------------------
74class IOCache(BaseCache):
75    assoc = 8
76    block_size = 64
77    latency = '50ns'
78    mshrs = 20
79    size = '1kB'
80    tgts_per_mshr = 12
81    addr_ranges = [AddrRange(0, size=mem_size)]
82    forward_snoops = False
83    is_top_level = True
84
85#cpu
86cpu = AtomicSimpleCPU(cpu_id=0)
87#the system
88mdesc = SysConfig(disk = 'linux-x86.img')
89system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
90system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
91system.iocache = IOCache()
92system.iocache.cpu_side = system.iobus.master
93system.iocache.mem_side = system.membus.slave
94
95system.cpu = cpu
96#create the l1/l2 bus
97system.toL2Bus = CoherentBus()
98
99#connect up the l2 cache
100system.l2c = L2(size='4MB', assoc=8)
101system.l2c.cpu_side = system.toL2Bus.master
102system.l2c.mem_side = system.membus.slave
103
104#connect up the cpu and l1s
105cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
106                            L1(size = '32kB', assoc = 4),
107                            PageTableWalkerCache(),
108                            PageTableWalkerCache())
109# create the interrupt controller
110cpu.createInterruptController()
111# connect cpu level-1 caches to shared level-2 cache
112cpu.connectAllPorts(system.toL2Bus, system.membus)
113cpu.clock = '2GHz'
114
115root = Root(full_system=True, system=system)
116m5.ticks.setGlobalFrequency('1THz')
117
118