pc-o3-timing.py revision 9263:066099902102 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34
35mem_size = '128MB'
36
37# --------------------
38# Base L1 Cache
39# ====================
40
41class L1(BaseCache):
42    hit_latency = '1ns'
43    response_latency = '1ns'
44    block_size = 64
45    mshrs = 4
46    tgts_per_mshr = 20
47    is_top_level = True
48
49# ----------------------
50# Base L2 Cache
51# ----------------------
52
53class L2(BaseCache):
54    block_size = 64
55    hit_latency = '10ns'
56    response_latency = '10ns'
57    mshrs = 92
58    tgts_per_mshr = 16
59    write_buffers = 8
60
61# ---------------------
62# Page table walker cache
63# ---------------------
64class PageTableWalkerCache(BaseCache):
65    assoc = 2
66    block_size = 64
67    hit_latency = '1ns'
68    response_latency = '1ns'
69    mshrs = 10
70    size = '1kB'
71    tgts_per_mshr = 12
72
73# ---------------------
74# I/O Cache
75# ---------------------
76class IOCache(BaseCache):
77    assoc = 8
78    block_size = 64
79    hit_latency = '50ns'
80    response_latency = '50ns'
81    mshrs = 20
82    size = '1kB'
83    tgts_per_mshr = 12
84    addr_ranges = [AddrRange(0, size=mem_size)]
85    forward_snoops = False
86
87#cpu
88cpu = DerivO3CPU(cpu_id=0)
89#the system
90mdesc = SysConfig(disk = 'linux-x86.img')
91system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
92system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
93system.iocache = IOCache()
94system.iocache.cpu_side = system.iobus.master
95system.iocache.mem_side = system.membus.slave
96
97system.cpu = cpu
98#create the l1/l2 bus
99system.toL2Bus = CoherentBus()
100
101#connect up the l2 cache
102system.l2c = L2(size='4MB', assoc=8)
103system.l2c.cpu_side = system.toL2Bus.master
104system.l2c.mem_side = system.membus.slave
105
106#connect up the cpu and l1s
107cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
108                            L1(size = '32kB', assoc = 4),
109                            PageTableWalkerCache(),
110                            PageTableWalkerCache())
111# create the interrupt controller
112cpu.createInterruptController()
113# connect cpu level-1 caches to shared level-2 cache
114cpu.connectAllPorts(system.toL2Bus, system.membus)
115cpu.clock = '2GHz'
116
117root = Root(full_system=True, system=system)
118m5.ticks.setGlobalFrequency('1THz')
119
120