o3-timing.py revision 9381:ffec48040ac1 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34cpu = DerivO3CPU(cpu_id=0)
35cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
36                              L1Cache(size = '256kB'),
37                              L2Cache(size = '2MB'))
38# @todo Note that the L2 latency here is unmodified and 2 cycles,
39# should set hit latency and response latency to 20 cycles as for
40# other scripts
41cpu.clock = '2GHz'
42
43system = System(cpu = cpu,
44                physmem = SimpleDRAM(),
45                membus = CoherentBus(),
46                mem_mode = "timing")
47system.system_port = system.membus.slave
48system.physmem.port = system.membus.master
49# create the interrupt controller
50cpu.createInterruptController()
51cpu.connectAllPorts(system.membus)
52
53root = Root(full_system = False, system = system)
54