o3-timing.py revision 10406 
1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
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38#
39# Authors: Andreas Hansson
40
41from m5.objects import *
42from m5.defines import buildEnv
43from base_config import *
44from arm_generic import *
45from O3_ARM_v7a import O3_ARM_v7a_3
46
47# If we are running ARM regressions, use a more sensible CPU
48# configuration. This makes the results more meaningful, and also
49# increases the coverage of the regressions.
50if buildEnv['TARGET_ISA'] == "arm":
51    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
52                                   cpu_class=O3_ARM_v7a_3).create_root()
53else:
54    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
55                                   cpu_class=DerivO3CPU).create_root()
56