o3-timing.py revision 4444
14030Sktlim@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 23096Sstever@eecs.umich.edu# All rights reserved. 33096Sstever@eecs.umich.edu# 43096Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53096Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 63096Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73096Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83096Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93096Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103096Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113096Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123096Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133096Sstever@eecs.umich.edu# this software without specific prior written permission. 143096Sstever@eecs.umich.edu# 153096Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163096Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173096Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183096Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193096Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203096Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213096Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223096Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233096Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243096Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253096Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263096Sstever@eecs.umich.edu# 273096Sstever@eecs.umich.edu# Authors: Steve Reinhardt 283096Sstever@eecs.umich.edu 293096Sstever@eecs.umich.eduimport m5 303096Sstever@eecs.umich.edufrom m5.objects import * 313096Sstever@eecs.umich.edum5.AddToPath('../configs/common') 323096Sstever@eecs.umich.edu 333096Sstever@eecs.umich.educlass MyCache(BaseCache): 343096Sstever@eecs.umich.edu assoc = 2 353096Sstever@eecs.umich.edu block_size = 64 364444Ssaidi@eecs.umich.edu latency = '1ns' 373096Sstever@eecs.umich.edu mshrs = 10 383096Sstever@eecs.umich.edu tgts_per_mshr = 5 393096Sstever@eecs.umich.edu 404030Sktlim@umich.educpu = DerivO3CPU(cpu_id=0) 413096Sstever@eecs.umich.educpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 423096Sstever@eecs.umich.edu MyCache(size = '2MB')) 434390Sktlim@umich.educpu.clock = '2GHz' 443096Sstever@eecs.umich.edu 453096Sstever@eecs.umich.edusystem = System(cpu = cpu, 463096Sstever@eecs.umich.edu physmem = PhysicalMemory(), 473096Sstever@eecs.umich.edu membus = Bus()) 483096Sstever@eecs.umich.edusystem.physmem.port = system.membus.port 493096Sstever@eecs.umich.educpu.connectMemPorts(system.membus) 503096Sstever@eecs.umich.edu 513096Sstever@eecs.umich.eduroot = Root(system = system) 52