o3-timing.py revision 4444
14030Sktlim@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
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273096Sstever@eecs.umich.edu# Authors: Steve Reinhardt
283096Sstever@eecs.umich.edu
293096Sstever@eecs.umich.eduimport m5
303096Sstever@eecs.umich.edufrom m5.objects import *
313096Sstever@eecs.umich.edum5.AddToPath('../configs/common')
323096Sstever@eecs.umich.edu
333096Sstever@eecs.umich.educlass MyCache(BaseCache):
343096Sstever@eecs.umich.edu    assoc = 2
353096Sstever@eecs.umich.edu    block_size = 64
364444Ssaidi@eecs.umich.edu    latency = '1ns'
373096Sstever@eecs.umich.edu    mshrs = 10
383096Sstever@eecs.umich.edu    tgts_per_mshr = 5
393096Sstever@eecs.umich.edu
404030Sktlim@umich.educpu = DerivO3CPU(cpu_id=0)
413096Sstever@eecs.umich.educpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
423096Sstever@eecs.umich.edu                              MyCache(size = '2MB'))
434390Sktlim@umich.educpu.clock = '2GHz'
443096Sstever@eecs.umich.edu
453096Sstever@eecs.umich.edusystem = System(cpu = cpu,
463096Sstever@eecs.umich.edu                physmem = PhysicalMemory(),
473096Sstever@eecs.umich.edu                membus = Bus())
483096Sstever@eecs.umich.edusystem.physmem.port = system.membus.port
493096Sstever@eecs.umich.educpu.connectMemPorts(system.membus)
503096Sstever@eecs.umich.edu
513096Sstever@eecs.umich.eduroot = Root(system = system)
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