o3-timing.py revision 3096
13096Sstever@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
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273096Sstever@eecs.umich.edu# Authors: Steve Reinhardt
283096Sstever@eecs.umich.edu
293096Sstever@eecs.umich.eduimport m5
303096Sstever@eecs.umich.edufrom m5.objects import *
313096Sstever@eecs.umich.edum5.AddToPath('../configs/common')
323096Sstever@eecs.umich.edufrom FullO3Config import *
333096Sstever@eecs.umich.edu
343096Sstever@eecs.umich.educlass MyCache(BaseCache):
353096Sstever@eecs.umich.edu    assoc = 2
363096Sstever@eecs.umich.edu    block_size = 64
373096Sstever@eecs.umich.edu    latency = 1
383096Sstever@eecs.umich.edu    mshrs = 10
393096Sstever@eecs.umich.edu    tgts_per_mshr = 5
403096Sstever@eecs.umich.edu
413096Sstever@eecs.umich.educpu = DetailedO3CPU()
423096Sstever@eecs.umich.educpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
433096Sstever@eecs.umich.edu                              MyCache(size = '2MB'))
443096Sstever@eecs.umich.educpu.mem = cpu.dcache
453096Sstever@eecs.umich.edu
463096Sstever@eecs.umich.edusystem = System(cpu = cpu,
473096Sstever@eecs.umich.edu                physmem = PhysicalMemory(),
483096Sstever@eecs.umich.edu                membus = Bus())
493096Sstever@eecs.umich.edusystem.physmem.port = system.membus.port
503096Sstever@eecs.umich.educpu.connectMemPorts(system.membus)
513096Sstever@eecs.umich.edu
523096Sstever@eecs.umich.eduroot = Root(system = system)
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