o3-timing-ruby.py revision 9793:6e6cefc1db1f
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32m5.util.addToPath('../configs/topologies') 33 34 35import ruby_config 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 37 38cpu = DerivO3CPU(cpu_id=0) 39 40system = System(cpu = cpu, 41 physmem = ruby_memory, 42 membus = CoherentBus(), 43 mem_mode = "timing", 44 clk_domain = SrcClockDomain(clock = '1GHz')) 45 46# Create a seperate clock domain for components that should run at 47# CPUs frequency 48system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 49 50system.physmem.port = system.membus.master 51# create the interrupt controller 52cpu.createInterruptController() 53cpu.connectAllPorts(system.membus) 54 55# Connect the system port for loading of binaries etc 56system.system_port = system.membus.slave 57 58root = Root(full_system = False, system = system) 59