o3-timing-ruby.py revision 8801 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
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11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32
33
34import ruby_config
35ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
36
37cpu = DerivO3CPU(cpu_id=0)
38cpu.clock = '2GHz'
39
40system = System(cpu = cpu,
41                physmem = ruby_memory,
42                membus = Bus())
43system.physmem.port = system.membus.port
44cpu.connectAllPorts(system.membus)
45
46root = Root(full_system = False, system = system)
47