o3-timing-ruby.py revision 11670:6ce719503eae
111176Sshingarov@labware.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 211274Sshingarov@labware.com# All rights reserved. 311176Sshingarov@labware.com# 411176Sshingarov@labware.com# Redistribution and use in source and binary forms, with or without 511176Sshingarov@labware.com# modification, are permitted provided that the following conditions are 611176Sshingarov@labware.com# met: redistributions of source code must retain the above copyright 711176Sshingarov@labware.com# notice, this list of conditions and the following disclaimer; 811176Sshingarov@labware.com# redistributions in binary form must reproduce the above copyright 911176Sshingarov@labware.com# notice, this list of conditions and the following disclaimer in the 1011176Sshingarov@labware.com# documentation and/or other materials provided with the distribution; 1111176Sshingarov@labware.com# neither the name of the copyright holders nor the names of its 1211176Sshingarov@labware.com# contributors may be used to endorse or promote products derived from 1311176Sshingarov@labware.com# this software without specific prior written permission. 1411176Sshingarov@labware.com# 1511176Sshingarov@labware.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1611176Sshingarov@labware.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1711176Sshingarov@labware.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1811176Sshingarov@labware.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1911176Sshingarov@labware.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2011176Sshingarov@labware.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2111176Sshingarov@labware.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2211176Sshingarov@labware.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2311176Sshingarov@labware.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2411176Sshingarov@labware.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2511176Sshingarov@labware.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2611176Sshingarov@labware.com# 2711176Sshingarov@labware.com# Authors: Steve Reinhardt 2811176Sshingarov@labware.com 2911176Sshingarov@labware.comimport m5 3011176Sshingarov@labware.comfrom m5.objects import * 3111176Sshingarov@labware.comm5.util.addToPath('../configs/common') 3211176Sshingarov@labware.com 3311176Sshingarov@labware.com 3411176Sshingarov@labware.comimport ruby_config 3511176Sshingarov@labware.comruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) 3611176Sshingarov@labware.com 3711176Sshingarov@labware.comcpu = DerivO3CPU(cpu_id=0) 3811176Sshingarov@labware.com 3911176Sshingarov@labware.comsystem = System(cpu = cpu, 4011176Sshingarov@labware.com physmem = ruby_memory, 4111176Sshingarov@labware.com membus = SystemXBar(), 4211176Sshingarov@labware.com mem_mode = "timing", 4311176Sshingarov@labware.com clk_domain = SrcClockDomain(clock = '1GHz')) 4411176Sshingarov@labware.com 4511176Sshingarov@labware.com# Create a seperate clock domain for components that should run at 4611176Sshingarov@labware.com# CPUs frequency 4711176Sshingarov@labware.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 4811176Sshingarov@labware.com 4911176Sshingarov@labware.comsystem.physmem.port = system.membus.master 5011176Sshingarov@labware.com# create the interrupt controller 5111176Sshingarov@labware.comcpu.createInterruptController() 5211176Sshingarov@labware.comcpu.connectAllPorts(system.membus) 5311176Sshingarov@labware.com 5411176Sshingarov@labware.com# Connect the system port for loading of binaries etc 5511176Sshingarov@labware.comsystem.system_port = system.membus.slave 5611176Sshingarov@labware.com 5711176Sshingarov@labware.comroot = Root(full_system = False, system = system) 5811176Sshingarov@labware.com