o3-timing-ruby.py revision 8732
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
26166Ssteve.reinhardt@amd.com# All rights reserved.
36166Ssteve.reinhardt@amd.com#
46166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without
56166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are
66166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright
76166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer;
86166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright
96166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the
106166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution;
116166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its
126166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from
136166Ssteve.reinhardt@amd.com# this software without specific prior written permission.
146166Ssteve.reinhardt@amd.com#
156166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
166166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
176166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
186166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
196166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
206166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
216166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
226166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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246166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
256166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
266166Ssteve.reinhardt@amd.com#
276166Ssteve.reinhardt@amd.com# Authors: Steve Reinhardt
286166Ssteve.reinhardt@amd.com
296166Ssteve.reinhardt@amd.comimport m5
306166Ssteve.reinhardt@amd.comfrom m5.objects import *
316654Snate@binkert.orgm5.util.addToPath('../configs/common')
326166Ssteve.reinhardt@amd.com
336166Ssteve.reinhardt@amd.com
346289Snate@binkert.orgimport ruby_config
356870Sdrh5@cs.wisc.eduruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
366289Snate@binkert.org
376166Ssteve.reinhardt@amd.comcpu = DerivO3CPU(cpu_id=0)
386166Ssteve.reinhardt@amd.comcpu.clock = '2GHz'
396166Ssteve.reinhardt@amd.com
406166Ssteve.reinhardt@amd.comsystem = System(cpu = cpu,
416289Snate@binkert.org                physmem = ruby_memory,
426166Ssteve.reinhardt@amd.com                membus = Bus())
436166Ssteve.reinhardt@amd.comsystem.physmem.port = system.membus.port
447876Sgblack@eecs.umich.educpu.connectAllPorts(system.membus)
456166Ssteve.reinhardt@amd.com
468732Sandreas.hansson@arm.com# Connect the system port for loading of binaries etc
478732Sandreas.hansson@arm.comsystem.system_port = system.membus.port
488732Sandreas.hansson@arm.com
496166Ssteve.reinhardt@amd.comroot = Root(system = system)
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