o3-timing-ruby.py revision 6289
12810SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
212724Snikos.nikoleris@arm.com# All rights reserved.
38856Sandreas.hansson@arm.com#
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58856Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are
68856Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright
78856Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer;
88856Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright
98856Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the
108856Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution;
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138856Sandreas.hansson@arm.com# this software without specific prior written permission.
142810SN/A#
152810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
162810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
172810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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262810SN/A#
272810SN/A# Authors: Steve Reinhardt
282810SN/A
292810SN/Aimport m5
302810SN/Afrom m5.objects import *
312810SN/Am5.AddToPath('../configs/common')
322810SN/A
332810SN/A
342810SN/Aimport ruby_config
352810SN/Aruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
362810SN/A
372810SN/Acpu = DerivO3CPU(cpu_id=0)
382810SN/Acpu.clock = '2GHz'
392810SN/A
402810SN/Asystem = System(cpu = cpu,
4112724Snikos.nikoleris@arm.com                physmem = ruby_memory,
422810SN/A                membus = Bus())
432810SN/Asystem.physmem.port = system.membus.port
442810SN/Acpu.connectMemPorts(system.membus)
452810SN/A
462810SN/Aroot = Root(system = system)
472810SN/A