o3-timing-mp.py revision 9381:ffec48040ac1
19380SAndreas.Sandberg@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27926Sgblack@eecs.umich.edu# All rights reserved. 37926Sgblack@eecs.umich.edu# 49380SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 59380SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 69380SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 79380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 89380SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 99380SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 109380SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 119380SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 129380SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 137926Sgblack@eecs.umich.edu# this software without specific prior written permission. 147926Sgblack@eecs.umich.edu# 157926Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167926Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177926Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187926Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197926Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207926Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217926Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227926Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237926Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247926Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257926Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267926Sgblack@eecs.umich.edu# 277926Sgblack@eecs.umich.edu# Authors: Ron Dreslinski 287926Sgblack@eecs.umich.edu 297926Sgblack@eecs.umich.eduimport m5 307926Sgblack@eecs.umich.edufrom m5.objects import * 317926Sgblack@eecs.umich.edum5.util.addToPath('../configs/common') 327926Sgblack@eecs.umich.edufrom Caches import * 337926Sgblack@eecs.umich.edu 347926Sgblack@eecs.umich.edunb_cores = 4 357926Sgblack@eecs.umich.educpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 369380SAndreas.Sandberg@ARM.com 377926Sgblack@eecs.umich.edu# system simulated 387926Sgblack@eecs.umich.edusystem = System(cpu = cpus, 399380SAndreas.Sandberg@ARM.com physmem = SimpleDRAM(), 407926Sgblack@eecs.umich.edu membus = CoherentBus(), 419380SAndreas.Sandberg@ARM.com mem_mode = "timing") 4211837Swendy.elsasser@arm.com 439380SAndreas.Sandberg@ARM.com# l2cache & bus 447926Sgblack@eecs.umich.edusystem.toL2Bus = CoherentBus(clock = '2GHz') 45system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 46system.l2c.cpu_side = system.toL2Bus.master 47 48# connect l2c to membus 49system.l2c.mem_side = system.membus.slave 50 51# add L1 caches 52for cpu in cpus: 53 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), 54 L1Cache(size = '32kB', assoc = 4)) 55 # create the interrupt controller 56 cpu.createInterruptController() 57 # connect cpu level-1 caches to shared level-2 cache 58 cpu.connectAllPorts(system.toL2Bus, system.membus) 59 cpu.clock = '2GHz' 60 61# connect memory to membus 62system.physmem.port = system.membus.master 63 64# connect system port to membus 65system.system_port = system.membus.slave 66 67# ----------------------- 68# run simulation 69# ----------------------- 70 71root = Root( full_system = False, system = system ) 72root.system.mem_mode = 'timing' 73#root.trace.flags="Bus Cache" 74#root.trace.flags = "BusAddrRanges" 75