o3-timing-mp.py revision 9036:6385cf85bf12
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32 33# -------------------- 34# Base L1 Cache 35# ==================== 36 37class L1(BaseCache): 38 latency = '1ns' 39 block_size = 64 40 mshrs = 4 41 tgts_per_mshr = 20 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 50 latency = '10ns' 51 mshrs = 92 52 tgts_per_mshr = 16 53 write_buffers = 8 54 55nb_cores = 4 56cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 57 58# system simulated 59system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) 60 61# l2cache & bus 62system.toL2Bus = CoherentBus() 63system.l2c = L2(size='4MB', assoc=8) 64system.l2c.cpu_side = system.toL2Bus.master 65 66# connect l2c to membus 67system.l2c.mem_side = system.membus.slave 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) 73 # create the interrupt controller 74 cpu.createInterruptController() 75 # connect cpu level-1 caches to shared level-2 cache 76 cpu.connectAllPorts(system.toL2Bus, system.membus) 77 cpu.clock = '2GHz' 78 79# connect memory to membus 80system.physmem.port = system.membus.master 81 82# connect system port to membus 83system.system_port = system.membus.slave 84 85# ----------------------- 86# run simulation 87# ----------------------- 88 89root = Root( full_system = False, system = system ) 90root.system.mem_mode = 'timing' 91#root.trace.flags="Bus Cache" 92#root.trace.flags = "BusAddrRanges" 93