o3-timing-mp.py revision 8801:1a84c6a81299 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32
33# --------------------
34# Base L1 Cache
35# ====================
36
37class L1(BaseCache):
38    latency = '1ns'
39    block_size = 64
40    mshrs = 4
41    tgts_per_mshr = 20
42    is_top_level = True
43
44# ----------------------
45# Base L2 Cache
46# ----------------------
47
48class L2(BaseCache):
49    block_size = 64
50    latency = '10ns'
51    mshrs = 92
52    tgts_per_mshr = 16
53    write_buffers = 8
54
55nb_cores = 4
56cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
57
58# system simulated
59system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
60Bus())
61
62# l2cache & bus
63system.toL2Bus = Bus()
64system.l2c = L2(size='4MB', assoc=8)
65system.l2c.cpu_side = system.toL2Bus.port
66system.l2c.num_cpus = nb_cores
67
68# connect l2c to membus
69system.l2c.mem_side = system.membus.port
70
71# add L1 caches
72for cpu in cpus:
73    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
74                                L1(size = '32kB', assoc = 4))
75    # connect cpu level-1 caches to shared level-2 cache
76    cpu.connectAllPorts(system.toL2Bus, system.membus)
77    cpu.clock = '2GHz'
78
79# connect memory to membus
80system.physmem.port = system.membus.port
81
82# connect system port to membus
83system.system_port = system.membus.port
84
85# -----------------------
86# run simulation
87# -----------------------
88
89root = Root( full_system = False, system = system )
90root.system.mem_mode = 'timing'
91#root.trace.flags="Bus Cache"
92#root.trace.flags = "BusAddrRanges"
93