o3-timing-mp.py revision 3223:a2b6fa575c05
1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31m5.AddToPath('../configs/common') 32 33# -------------------- 34# Base L1 Cache 35# ==================== 36 37class L1(BaseCache): 38 latency = 1 39 block_size = 64 40 mshrs = 4 41 tgts_per_mshr = 8 42 protocol = CoherenceProtocol(protocol='moesi') 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 50 latency = 100 51 mshrs = 92 52 tgts_per_mshr = 16 53 write_buffers = 8 54 55nb_cores = 4 56cpus = [ DerivO3CPU() for i in xrange(nb_cores) ] 57 58# system simulated 59system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 60Bus()) 61 62# l2cache & bus 63system.toL2Bus = Bus() 64system.l2c = L2(size='4MB', assoc=8) 65system.l2c.cpu_side = system.toL2Bus.port 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.port 69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) 74 cpu.mem = cpu.dcache 75 # connect cpu level-1 caches to shared level-2 cache 76 cpu.connectMemPorts(system.toL2Bus) 77 78# connect memory to membus 79system.physmem.port = system.membus.port 80 81 82# ----------------------- 83# run simulation 84# ----------------------- 85 86root = Root( system = system ) 87root.system.mem_mode = 'timing' 88root.trace.flags="Bus Cache" 89#root.trace.flags = "BusAddrRanges" 90