o3-timing-mp.py revision 3200:4b072dcc7a57 
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32from FullO3Config import *
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39    latency = 1
40    block_size = 64
41    mshrs = 4
42    tgts_per_mshr = 8
43    protocol = CoherenceProtocol(protocol='moesi')
44
45# ----------------------
46# Base L2 Cache
47# ----------------------
48
49class L2(BaseCache):
50    block_size = 64
51    latency = 100
52    mshrs = 92
53    tgts_per_mshr = 16
54    write_buffers = 8
55
56nb_cores = 4
57cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
58
59# system simulated
60system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
61Bus())
62
63# l2cache & bus
64system.toL2Bus = Bus()
65system.l2c = L2(size='4MB', assoc=8)
66system.l2c.cpu_side = system.toL2Bus.port
67
68# connect l2c to membus
69system.l2c.mem_side = system.membus.port
70
71# add L1 caches
72for cpu in cpus:
73    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
74                                L1(size = '32kB', assoc = 4))
75    cpu.mem = cpu.dcache
76    # connect cpu level-1 caches to shared level-2 cache
77    cpu.connectMemPorts(system.toL2Bus)
78
79# connect memory to membus
80system.physmem.port = system.membus.port
81
82
83# -----------------------
84# run simulation
85# -----------------------
86
87root = Root( system = system )
88root.system.mem_mode = 'timing'
89#root.trace.flags="Bus Cache"
90#root.trace.flags = "BusAddrRanges"
91